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BUFFER/LEVEL TRANSLATOR. SI53301 Datasheet

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BUFFER/LEVEL TRANSLATOR. SI53301 Datasheet






SI53301 TRANSLATOR. Datasheet pdf. Equivalent




SI53301 TRANSLATOR. Datasheet pdf. Equivalent





Part

SI53301

Description

1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR



Feature


Si53301 1:6 LOW JITTER UNIVERSAL BUFFER /LEVEL TRANSLATOR WITH 2:1 INPUT MUX F eatures  6 differential or 12 LVCMO S outputs  Loss of signal (LOS) moni tors for  Ultra-low additive jitter : 45 fs rms loss of input clock  W ide frequency range: 1 to 725 MHz  I ndependent VDD and VDDO :  Universa l any-format input with pin 1.8/2.5/3. 3 V selectable output formats.
Manufacture

Silicon Laboratories

Datasheet
Download SI53301 Datasheet


Silicon Laboratories SI53301

SI53301;  1.2/1.5 V LVCMOS output support LVPECL, low power LVPECL, LVDS,  Selectable LVCMOS drive strength to CM L, HCSL, LVCMOS tailor jitter and EMI performance  2:1 input mux  Sma ll size: 32-QFN (5 mm x 5 mm)  Glit chless input clock switching  RoHS compliant, Pb-free  Synchronous out put enable  Industrial temperature range:  Output clock division: /1,.


Silicon Laboratories SI53301

/2, /4 –40 to +85 °C Applications  High-speed clock distribution  E thernet switch/router  Optical Trans port Network (OTN)  SONET/SDH  PC I Express Gen 1/2/3  Storage  Te lecom  Industrial  Servers  Ba ckplane clock distribution Description The Si53301 is an ultra low jitter six output differential buffer with pin-se lectable output clock signal format and d.


Silicon Laboratories SI53301

ivider selection. The Si53301 features a 2:1 input mux with glitchless switchin g, making it ideal for redundant clocki ng applications. The Si53301 utilizes S ilicon Laboratories' advanced CMOS tech nology to fanout clocks from 1 to 725 M Hz with guaranteed low additive jitter, low skew, and low propagation delay va riability. The Si53301 features minimal cross-talk and pr.

Part

SI53301

Description

1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR



Feature


Si53301 1:6 LOW JITTER UNIVERSAL BUFFER /LEVEL TRANSLATOR WITH 2:1 INPUT MUX F eatures  6 differential or 12 LVCMO S outputs  Loss of signal (LOS) moni tors for  Ultra-low additive jitter : 45 fs rms loss of input clock  W ide frequency range: 1 to 725 MHz  I ndependent VDD and VDDO :  Universa l any-format input with pin 1.8/2.5/3. 3 V selectable output formats.
Manufacture

Silicon Laboratories

Datasheet
Download SI53301 Datasheet




 SI53301
Si53301
1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX
Features
6 differential or 12 LVCMOS outputs Loss of signal (LOS) monitors for
Ultra-low additive jitter: 45 fs rms
loss of input clock
Wide frequency range: 1 to 725 MHz Independent VDD and VDDO :
Universal any-format input with pin
1.8/2.5/3.3 V
selectable output formats
1.2/1.5 V LVCMOS output support
LVPECL, low power LVPECL, LVDS, Selectable LVCMOS drive strength to
CML, HCSL, LVCMOS
tailor jitter and EMI performance
2:1 input mux
Small size: 32-QFN (5 mm x 5 mm)
Glitchless input clock switching
RoHS compliant, Pb-free
Synchronous output enable
Industrial temperature range:
Output clock division: /1, /2, /4
–40 to +85 °C
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53301 is an ultra low jitter six output differential buffer with pin-selectable
output clock signal format and divider selection. The Si53301 features a 2:1 input
mux with glitchless switching, making it ideal for redundant clocking applications.
The Si53301 utilizes Silicon Laboratories' advanced CMOS technology to fanout
clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low
propagation delay variability. The Si53301 features minimal cross-talk and
provides superior supply noise rejection, simplifying low jitter clock distribution in
noisy environments. Independent core and output bank supply pins provide
integrated level translation without the need for external circuitry.
Functional Block Diagram
Ordering Information:
See page 29.
Pin Assignments
Si53301
DIVA
SFOUTA[1]
SFOUTA[0]
Q0
Q0
GND
VDD
CLK_SEL
1
2
3
4
5
6
7
8
GND
PAD
24 DIVB
23 SFOUTB[1]
22 SFOUTB[0]
21 Q5
20 Q5
19 VDDOB
18 VDDOA
17 VREF
Patents pending
Vref
LOS0
LOS1
CLK0
/CLK0
CLK1
/CLK1
CLK_SEL
VDD
Vref
Generator
LOS
Monitor
Power
Supply
Filtering
DivA
BANK A
Switching
Logic
DivB
BANK B
DIVA
VDDOA
SFOUTA[1:0]
OEA
Q0, Q1, Q2
/Q0, /Q1, /Q2
DIVB
VDDOB
SFOUTB[1:0]
OEB
Q3, Q4, Q5
/Q3, /Q4, /Q5
Rev. 1.1 6/14
Copyright © 2014 by Silicon Laboratories
Si53301




 SI53301
TABLE OF CONTENTS
Si53301
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3. Input Clock Voltage Reference (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5. Glitchless Clock Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6. Synchronous Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7. Flexible Output Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.9. Loss of Signal (LOS) Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.10. Power Supply (VDD and VDDOX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.11. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.12. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.13. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.14. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.15. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3. Pin Description: 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1. 5x5 mm 32-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6.1. 5x5 mm 32-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1. Si53301 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Rev. 1.1
2




 SI53301
Si53301
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range*
Symbol
TA
VDD
Test Condition
LVDS, CML
Min Typ Max Unit
–40 —
85 °C
1.71 1.8 1.89 V
2.38 2.5 2.63 V
2.97 3.3 3.63 V
LVPECL, low power LVPECL,
2.38
2.5
2.63 V
LVCMOS
2.97 3.3 3.63 V
HCSL
2.97 3.3 3.63 V
Output Buffer Supply
Voltage*
VDDOX
LVDS, CML, LVCMOS
1.71 1.8 1.89 V
2.38 2.5 2.63 V
2.97 3.3 3.63 V
LVPECL, low power LVPECL 2.38 2.5 2.63 V
2.97 3.3 3.63 V
HCSL
2.97 3.3 3.63 V
*Note: Core supply VDD and output buffer supplies VDDO are independent. LVCMOS clock input is not supported for VDD =
1.8V but is supported for LVCMOS clock output for VDDOX = 1.8V. LVCMOS outputs at 1.5V and 1.2V can be
supported via a simple resistor divider network. See “2.11.1. LVCMOS Output Termination To Support 1.5V and 1.2V”
Table 2. Input Clock Specifications
(VDD=1.8 V 5%, 2.5 V 5%, or 3.3 V 10%, TA=–40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Differential Input Common
Mode Voltage
VCM
VDD = 2.5 V5%, 3.3 V10%
0.05
— —V
Differential Input Swing
(peak-to-peak)
VIN
0.2 — 2.2 V
LVCMOS Input High Volt-
age
VIH
VDD = 2.5 V5%, 3.3 V10% VDD x 0.7
—V
LVCMOS Input Low Volt- VIL VDD = 2.5 V5%, 3.3 V10%
age
— VDD x V
0.3
Input Capacitance
CIN CLK0 and CLK1 pins with — 5 — pF
respect to GND
Rev. 1.1
3



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