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BUFFER/LEVEL TRANSLATOR. SI53304 Datasheet

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BUFFER/LEVEL TRANSLATOR. SI53304 Datasheet






SI53304 TRANSLATOR. Datasheet pdf. Equivalent




SI53304 TRANSLATOR. Datasheet pdf. Equivalent





Part

SI53304

Description

1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR



Feature


Si53304 1:6 LOW JITTER UNIVERSAL BUFFER /LEVEL TRANSLATOR WITH 2:1 INPUT MUX AN D INDIVIDUAL OE Features ļ® 6 differ ential or 12 LVCMOS outputs ļ® Indepen dent VDD and VDDO: ļ® Ultra-low addit ive jitter: 45 fs rms 1.8/2.5/3.3 V ļ ® Wide frequency range: 1 to 725 MHz ļ ® 1.2/1.5 V LVCMOS output support ļ® Any-format input with pin selectable ļ ® Excellent power supply noise .
Manufacture

Silicon Laboratories

Datasheet
Download SI53304 Datasheet


Silicon Laboratories SI53304

SI53304; output formats: LVPECL, Low Power rejec tion (PSRR) LVPECL, LVDS, CML, HCSL, ļ® Selectable LVCMOS drive strength to LVCMOS tailor jitter and EMI perform ance ļ® 2:1 mux with hot-swappable in puts ļ® Small size: 32-QFN (5x5 mm) ļ ® Glitchless input clock switching ļ ® RoHS compliant, Pb-free ļ® Synchron ous output enable ļ® Industrial tempe rature range: ļ® Individual outp.


Silicon Laboratories SI53304

ut enable ā€“40 to +85 Ā°C Application s ļ® High-speed clock distribution ļ® Ethernet switch/router ļ® Optical Tra nsport Network (OTN) ļ® SONET/SDH ļ® PCI Express Gen 1/2/3 ļ® Storage ļ® Telecom ļ® Industrial ļ® Servers ļ® Backplane clock distribution Descripti on The Si53304 is an ultra low jitter s ix output differential buffer with pin- selectable output clock signal format and.


Silicon Laboratories SI53304

individual OE. The Si53304 features a 2 :1 mux with glitchless switching, makin g it ideal for redundant clocking appli cations. The Si53304 utilizes Silicon L aboratories' advanced CMOS technology t o fanout clocks from 1 to 725 MHz with guaranteed low additive jitter, low ske w, and low propagation delay variabilit y. The Si53304 features minimal cross-t alk and provides s.

Part

SI53304

Description

1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR



Feature


Si53304 1:6 LOW JITTER UNIVERSAL BUFFER /LEVEL TRANSLATOR WITH 2:1 INPUT MUX AN D INDIVIDUAL OE Features ļ® 6 differ ential or 12 LVCMOS outputs ļ® Indepen dent VDD and VDDO: ļ® Ultra-low addit ive jitter: 45 fs rms 1.8/2.5/3.3 V ļ ® Wide frequency range: 1 to 725 MHz ļ ® 1.2/1.5 V LVCMOS output support ļ® Any-format input with pin selectable ļ ® Excellent power supply noise .
Manufacture

Silicon Laboratories

Datasheet
Download SI53304 Datasheet




 SI53304
Si53304
1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE
Features
ļ® 6 differential or 12 LVCMOS outputs ļ® Independent VDD and VDDO:
ļ® Ultra-low additive jitter: 45 fs rms
1.8/2.5/3.3 V
ļ® Wide frequency range: 1 to 725 MHz ļ® 1.2/1.5 V LVCMOS output support
ļ® Any-format input with pin selectable ļ® Excellent power supply noise
output formats: LVPECL, Low Power rejection (PSRR)
LVPECL, LVDS, CML, HCSL,
ļ® Selectable LVCMOS drive strength to
LVCMOS
tailor jitter and EMI performance
ļ® 2:1 mux with hot-swappable inputs ļ® Small size: 32-QFN (5x5 mm)
ļ® Glitchless input clock switching
ļ® RoHS compliant, Pb-free
ļ® Synchronous output enable
ļ® Industrial temperature range:
ļ® Individual output enable
ā€“40 to +85 Ā°C
Applications
ļ® High-speed clock distribution
ļ® Ethernet switch/router
ļ® Optical Transport Network (OTN)
ļ® SONET/SDH
ļ® PCI Express Gen 1/2/3
ļ® Storage
ļ® Telecom
ļ® Industrial
ļ® Servers
ļ® Backplane clock distribution
Description
The Si53304 is an ultra low jitter six output differential buffer with pin-selectable
output clock signal format and individual OE. The Si53304 features a 2:1 mux with
glitchless switching, making it ideal for redundant clocking applications. The
Si53304 utilizes Silicon Laboratories' advanced CMOS technology to fanout
clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low
propagation delay variability. The Si53304 features minimal cross-talk and
provides superior supply noise rejection, simplifying low jitter clock distribution in
noisy environments. Independent core and output bank supply pins provide
integrated level translation without the need for external circuitry.
Functional Block Diagram
VREF
Vref
Generator
VDD
Power
Supply
Filtering
VDDOA
SFOUTA[1:0]
OE[2:0]
Ordering Information:
See page 28.
Pin Assignments
Si53304
OE0
SFOUTA[1]
SFOUTA[0]
Q0
Q0
GND
VDD
CLK_SEL
1
2
3
4
5
6
7
8
GND
PAD
24 OE5
23 SFOUTB[1]
22 SFOUTB[0]
21 Q5
20 Q5
19 VDDOB
18 VDDOA
17 VREF
Patents pending
CLK0
/CLK0
CLK1
/CLK1
CLK_SEL
Switching
Logic
BANK A
VDDOB
SFOUTB[1:0]
OE[5:3]
BANK B
Rev. 1.0 4/14
Copyright Ā© 2014 by Silicon Laboratories
Si53304




 SI53304
Si53304
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3. Input Clock Voltage Reference (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5. Glitchless Clock Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6. Synchronous Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8. Power Supply (VDD and VDDOX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.9. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.10. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.11. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.12. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.13. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1. 5x5 mm 32-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
5.1. 5x5 mm 32-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1. Si53304 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2 Rev. 1.0




 SI53304
Si53304
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range*
Symbol
TA
VDD
Test Condition
LVDS, CML
Min Typ Max Unit
ā€“40 ā€”
85 Ā°C
1.71 1.8 1.89 V
2.38 2.5 2.63 V
2.97 3.3 3.63 V
LVPECL, low power LVPECL,
2.38
2.5
2.63 V
LVCMOS
2.97 3.3 3.63 V
HCSL
2.97 3.3 3.63 V
Output Buffer Supply
Voltage*
VDDOX
LVDS, CML, LVCMOS
1.71 1.8 1.89 V
2.38 2.5 2.63 V
2.97 3.3 3.63 V
LVPECL, low power LVPECL 2.38 2.5 2.63 V
2.97 3.3 3.63 V
HCSL
2.97 3.3 3.63 V
*Note: Core supply VDD and output buffer supplies VDDO are independent. LVCMOS clock input is not supported for VDD =
1.8V but is supported for LVCMOS clock output for VDDOX = 1.8V. LVCMOS outputs at 1.5V and 1.2V can be
supported via a simple resistor divider network. See ā€œ2.9.1. LVCMOS Output Termination To Support 1.5V and 1.2Vā€
Table 2. Input Clock Specifications
(VDD=1.8 V ļ‚± 5%, 2.5 V ļ‚± 5%, or 3.3 V ļ‚± 10%, TA=ā€“40 to 85 Ā°C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Differential Input Common
Mode Voltage
VCM
VDD = 2.5 Vļ‚± 5%, 3.3 Vļ‚± 10%
0.05
ā€” ā€”V
Differential Input Swing
(peak-to-peak)
VIN
0.2 ā€” 2.2 V
LVCMOS Input High Volt-
age
VIH
VDD = 2.5 Vļ‚± 5%, 3.3 Vļ‚± 10% VDD x 0.7
ā€”
ā€”V
LVCMOS Input Low Volt- VIL VDD = 2.5 Vļ‚± 5%, 3.3 Vļ‚± 10%
age
ā€”
ā€” VDD x V
0.3
Input Capacitance
CIN CLK0 and CLK1 pins with ā€” 5 ā€” pF
respect to GND
Rev. 1.0
3



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