SI53306

Si53306 1:4 LOW-JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR Features  4 differential or 8 LVCMOS outputs  Independent VDD and VDDO :  Ultra-low additive jitter: 45 fs rms 1.8/2.5/3.3 V  Wide frequency range: 1 to 725 MHz  1.2/1.5 V LVCMOS output support  Any-format input with pin selectable  Selectable LVCMOS drive strength to output formats: LVPECL, low power tailor jitter and EMI performance LVPECL, LVDS, CML, HCSL, LVCMOS  Synchronous output enable  Small size: 16-QFN (3 mm x 3 mm)  RoHS compliant, Pb-free  Industrial temperature range: –40 to +85 °C Applications  High-speed clock distribution  Ethernet switch/router  Optical Transport Network (OTN)  SONET/SDH  PCI Express Gen 1/2/3  Storage  Telecom  Industrial  Servers  Backplane clock distribution Description The Si53306 is an ultra low jitter four output differential buffer with pin-selectable output clock signal format. The Si53306 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53306 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry. Functional Block Diagram Ordering Information: See page 24. Pin Assignments OE Q0 Q0 SFOUT0 13 14 15 16 VDD CL...