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BUFFER/LEVEL TRANSLATOR. SI53311 Datasheet

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BUFFER/LEVEL TRANSLATOR. SI53311 Datasheet






SI53311 TRANSLATOR. Datasheet pdf. Equivalent




SI53311 TRANSLATOR. Datasheet pdf. Equivalent





Part

SI53311

Description

1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR



Feature


Si53311 1:6 LOW JITTER UNIVERSAL BUFFER /LEVEL TRANSLATOR WITH 2:1 INPUT MUX (< 1.25 GHZ) Features  6 differential or 12 LVCMOS outputs  Low output-ou tput skew: <50 ps  Ultra-low additi ve jitter: 100 fs rms  Low propagati on delay variation:  Wide frequency range: <400 ps 1 MHz to 1.25 GHz Independent VDD and VDDO :  Any-f ormat input with pin selectable .
Manufacture

Silicon Laboratories

Datasheet
Download SI53311 Datasheet


Silicon Laboratories SI53311

SI53311; 1.8/2.5/3.3 V output formats: LVPECL, L ow Power  Excellent power supply noi se LVPECL, LVDS, CML, HCSL, rejection (PSRR) LVCMOS  Selectable LVCMOS drive strength to  2:1 mux with hot -swappable inputs tailor jitter and EM I performance  Asynchronous output enable  Output clock division: /1, / 2, /4  Small size: 32-QFN (5 mm x 5 mm)  RoHS compliant, Pb-free.


Silicon Laboratories SI53311

 Industrial temperature range: – 40 to +85 °C Ordering Information: Se e page 25. Applications  High-speed clock distribution  Ethernet switch /router  Optical Transport Network ( OTN)  SONET/SDH  PCI Express Gen 1/2/3  Storage  Telecom  Indu strial  Servers  Backplane clock distribution Description The Si53311 i s an ultra low jitter six output differenti.


Silicon Laboratories SI53311

al buffer with pin-selectable output clo ck signal format and divider selection. The Si53311 features a 2:1 mux, making it ideal for redundant clocking applic ations. The Si53311 utilizes Silicon La boratories' advanced CMOS technology to fanout clocks from 1 MHz to 1.25 GHz w ith guaranteed low additive jitter, low skew, and low propagation delay variab ility. The Si53311.

Part

SI53311

Description

1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR



Feature


Si53311 1:6 LOW JITTER UNIVERSAL BUFFER /LEVEL TRANSLATOR WITH 2:1 INPUT MUX (< 1.25 GHZ) Features  6 differential or 12 LVCMOS outputs  Low output-ou tput skew: <50 ps  Ultra-low additi ve jitter: 100 fs rms  Low propagati on delay variation:  Wide frequency range: <400 ps 1 MHz to 1.25 GHz Independent VDD and VDDO :  Any-f ormat input with pin selectable .
Manufacture

Silicon Laboratories

Datasheet
Download SI53311 Datasheet




 SI53311
Si53311
1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX (<1.25 GHZ)
Features
6 differential or 12 LVCMOS outputs Low output-output skew: <50 ps
Ultra-low additive jitter: 100 fs rms Low propagation delay variation:
Wide frequency range:
<400 ps
1 MHz to 1.25 GHz
Independent VDD and VDDO :
Any-format input with pin selectable 1.8/2.5/3.3 V
output formats: LVPECL, Low Power Excellent power supply noise
LVPECL, LVDS, CML, HCSL,
rejection (PSRR)
LVCMOS
Selectable LVCMOS drive strength to
2:1 mux with hot-swappable inputs
tailor jitter and EMI performance
Asynchronous output enable
Output clock division: /1, /2, /4
Small size: 32-QFN (5 mm x 5 mm)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Ordering Information:
See page 25.
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53311 is an ultra low jitter six output differential buffer with pin-selectable
output clock signal format and divider selection. The Si53311 features a 2:1 mux,
making it ideal for redundant clocking applications. The Si53311 utilizes Silicon
Laboratories' advanced CMOS technology to fanout clocks from 1 MHz to
1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay
variability. The Si53311 features minimal cross-talk and provides superior supply
noise rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation
without the need for external circuitry.
Pin Assignments
Si53311
DIVA
SFOUTA[1]
SFOUTA[0]
Q0
Q0
GND
VDD
CLK_SEL
1
2
3
4
5
6
7
8
GND
PAD
24 DIVB
23 SFOUTB[1]
22 SFOUTB[0]
21 Q5
20 Q5
19 VDDOB
18 VDDOA
17 VREF
Patents pending
Functional Block Diagram
VREF
Vref
Generator
Power
Supply
Filtering
CLK0
CLK0
CLK1
CLK1
CLK_SEL
DivA
Switching
Logic
DivB
DIVA
VDDOA
SFOUTA[1:0]
OEA
Q0, Q1, Q2
Q0, Q1, Q2
DIVB
VDDOB
SFOUTB[1:0]
OEB
Q3, Q4, Q5
Q3, Q4, Q5
Preliminary Rev. 0.4 10/12
Copyright © 2012 by Silicon Laboratories
Si53311
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.




 SI53311
Si53311
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5. Flexible Output Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7. Power Supply (VDD and VDDOX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.8. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.9. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.10. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.11. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.12. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3. Pin Description: 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1. 5x5 mm 32-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6.1. 5x5 mm 32-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1. Si53311 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2 Preliminary Rev. 0.4




 SI53311
Si53311
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Symbol
TA
Test Condition
Min Typ Max Unit
–40 —
85 °C
Supply Voltage Range*
VDD
LVDS, CML, HCSL, LVCMOS
1.71
1.8
1.89 V
LVPECL, low power LVPECL, 2.38 2.5 2.63 V
LVDS, CML, HCSL, LVCMOS
2.97
3.3
3.63 V
Output Buffer Supply
Voltage*
VDDO
LVDS, CML, HCSL, LVCMOS
1.71
1.89 V
LVPECL, low power LVPECL,
2.38
2.63 V
LVDS, CML, HCSL, LVCMOS
2.97
3.63 V
*Note: Core supply VDD and output buffer supplies VDDO are independent.
Table 2. Input Clock Specifications
(VDD=1.8 V 5%, 2.5 V 5%, or 3.3 V 10%, TA=–40 to 85 °C)
Parameter
Differential Input Common
Mode Voltage
Input Swing
(single-ended, peak-to-
peak)
Input Voltage High
Symbol
VCM
VIN
VIH
Test Condition
VDD = 2.5 V5%, 3.3 V10%
Min
0.05
0.1
VDD x
0.7
Typ
Max Unit
—V
1.1 V
—V
Input Voltage Low
VIL
— — VDD x V
0.3
Input Capacitance
CIN
— 5 — pF
Preliminary Rev. 0.4
3



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