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BUFFER/LEVEL TRANSLATOR. SI53315 Datasheet

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BUFFER/LEVEL TRANSLATOR. SI53315 Datasheet






SI53315 TRANSLATOR. Datasheet pdf. Equivalent




SI53315 TRANSLATOR. Datasheet pdf. Equivalent





Part

SI53315

Description

1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR



Feature


Si53315 1:10 LOW JITTER UNIVERSAL BUFFE R/LEVEL TRANSLATOR WITH 2:1 INPUT MUX A ND INDIVIDUAL OE (<1.25 GHZ) Features  10 differential or 20 LVCMOS outpu ts Low propagation delay variation:  Ultra-low additive jitter: 100 fs rms <400 ps  Wide frequency range: 1 MHz to 1.25 GHz  Independent VDD and VDDO : 1.8/2.5/3.3 V  Any-form at input with pin selectable .
Manufacture

Silicon Laboratories

Datasheet
Download SI53315 Datasheet


Silicon Laboratories SI53315

SI53315; Excellent power supply noise output fo rmats: LVPECL, Low Power rejection (PSR R) LVPECL, LVDS, CML, HCSL, LVCMOS Selectable LVCMOS drive strength to t ailor jitter and EMI performance  2 :1 mux with hot-swappable inputs  Sm all size: 44-QFN (7 mm x 7 mm)  Asy nchronous output enable  RoHS compl iant, Pb-free  Individual output en able  Industrial temperature.


Silicon Laboratories SI53315

range:  Low output-output skew: <50 ps –40 to +85 °C Applications  High-speed clock distribution  Ethe rnet switch/router  Optical Transpor t Network (OTN)  SONET/SDH  PCI E xpress Gen 1/2/3  Storage  Telec om  Industrial  Servers  Backp lane clock distribution Description Th e Si53315 is an ultra low jitter ten ou tput differential buffer with pin-selectabl.


Silicon Laboratories SI53315

e output clock signal format and individ ual OE. The Si53315 features a 2:1 mux, making it ideal for redundant clocking applications. The Si53315 utilizes Sil icon Laboratories' advanced CMOS techno logy to fanout clocks from 1 MHz to 1.2 5 GHz with guaranteed low additive jitt er, low skew, and low propagation delay variability. The Si53315 features mini mal cross-talk and.

Part

SI53315

Description

1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR



Feature


Si53315 1:10 LOW JITTER UNIVERSAL BUFFE R/LEVEL TRANSLATOR WITH 2:1 INPUT MUX A ND INDIVIDUAL OE (<1.25 GHZ) Features  10 differential or 20 LVCMOS outpu ts Low propagation delay variation:  Ultra-low additive jitter: 100 fs rms <400 ps  Wide frequency range: 1 MHz to 1.25 GHz  Independent VDD and VDDO : 1.8/2.5/3.3 V  Any-form at input with pin selectable .
Manufacture

Silicon Laboratories

Datasheet
Download SI53315 Datasheet




 SI53315
Si53315
1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE (<1.25 GHZ)
Features
10 differential or 20 LVCMOS outputsLow propagation delay variation:
Ultra-low additive jitter: 100 fs rms
<400 ps
Wide frequency range:
1 MHz to 1.25 GHz
Independent VDD and VDDO :
1.8/2.5/3.3 V
Any-format input with pin selectable Excellent power supply noise
output formats: LVPECL, Low Power rejection (PSRR)
LVPECL, LVDS, CML, HCSL,
LVCMOS
Selectable LVCMOS drive strength to
tailor jitter and EMI performance
2:1 mux with hot-swappable inputs Small size: 44-QFN (7 mm x 7 mm)
Asynchronous output enable
RoHS compliant, Pb-free
Individual output enable
Industrial temperature range:
Low output-output skew: <50 ps
–40 to +85 °C
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53315 is an ultra low jitter ten output differential buffer with pin-selectable
output clock signal format and individual OE. The Si53315 features a 2:1 mux,
making it ideal for redundant clocking applications. The Si53315 utilizes Silicon
Laboratories' advanced CMOS technology to fanout clocks from 1 MHz to
1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay
variability. The Si53315 features minimal cross-talk and provides superior supply
noise rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation
without the need for external circuitry.
Functional Block Diagram
Ordering Information:
See page 25.
Pin Assignments
Si53315
OE2 1
SFOUT[0] 2
OE1 3
Q2 4
Q2 5
GND 6
Q1 7
Q1 8
Q0 9
Q0 10
OE0 11
GND
PAD
33 OE7
32 SFOUT[1]
31 OE8
30 Q7
29 Q7
28 NC
27 Q8
26 Q8
25 Q9
24 Q9
23 OE9
Patents pending
VREF
Vref
Generator
Power
Supply
Filtering
CLK0
CLK0
CLK1
CLK1
CLK_SEL
Switching
Logic
VDDOA
OE[0:4]
Q0, Q1, Q2, Q3, Q4
Q0, Q1, Q2, Q3, Q4
SFOUT[1:0]
VDDOB
OE[5:9]
Q5, Q6, Q7, Q8, Q9
Q5, Q6, Q7, Q8, Q9
Preliminary Rev. 0.4 10/12
Copyright © 2012 by Silicon Laboratories
Si53315
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.




 SI53315
Si53315
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5. Power Supply (VDD and VDDOX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.7. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.9. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.10. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3. Pin Description: 44-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.1. 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6.1. 7x7 mm 44-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1. Si53315 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2 Preliminary Rev. 0.4




 SI53315
Si53315
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min Typ Max Unit
Ambient Operating
Temperature
Supply Voltage Range*
TA
–40 —
85 °C
VDD
LVDS, CML, HCSL, LVCMOS
1.71
1.8
1.89 V
LVPECL, low power LVPECL, 2.38 2.5 2.63 V
LVDS, CML, HCSL, LVCMOS
2.97
3.3
3.63 V
Output Buffer Supply
Voltage*
VDDO
LVDS, CML, HCSL, LVCMOS
1.71
1.89 V
LVPECL, low power LVPECL,
2.38
2.63 V
LVDS, CML, HCSL, LVCMOS
2.97
3.63 V
*Note: Core supply VDD and output buffer supplies VDDO are independent.
Table 2. Input Clock Specifications
(VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%, TA = –40 to 85 °C)
Parameter
Differential Input Common
Mode Voltage
Input Swing
(single-ended, peak-to-
peak)
Input Voltage High
Symbol
VCM
VIN
VIH
Test Condition
VDD = 2.5 V5%, 3.3 V10%
Min
0.05
0.1
VDD x
0.7
Typ
Max Unit
—V
1.1 V
—V
Input Voltage Low
VIL
— — VDD x V
0.3
Input Capacitance
CIN
— 5 — pF
Preliminary Rev. 0.4
3



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