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Clock Buffers. SI53320 Datasheet

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Clock Buffers. SI53320 Datasheet






SI53320 Buffers. Datasheet pdf. Equivalent




SI53320 Buffers. Datasheet pdf. Equivalent





Part

SI53320

Description

Low-Jitter LVPECL Fanout Clock Buffers



Feature


Si53320-28 Data Sheet Low-Jitter LVPECL Fanout Clock Buffers with up to 10 LVP ECL Outputs from Any-Format Input and W ide Frequency Range from DC up to 1250 MHz The Si53320–28 family of LVPECL f anout buffers is ideal for clock/data d istribution and redundant clocking appl ications. These devices feature typical ultra-low jitter characteristics of 50 fs and operate over.
Manufacture

Silicon Laboratories

Datasheet
Download SI53320 Datasheet


Silicon Laboratories SI53320

SI53320; a wide frequency range from dc to 725/1 250 MHz. Builtin LDOs deliver high PSRR performance and reduce the need for ex ternal components, simplifying low-jitt er clock distribution in noisy environm ents. The Si53320–28 family is availa ble in multiple configurations, with so me versions offering a selectable input clock using a 2:1 input mux. Other fea tures include indepe.


Silicon Laboratories SI53320

ndent output enable and built-in format translation. These buffers can be paire d with the Si534x clocks and Si5xx osci llators to deliver end-to-end clock tre e performance. KEY FEATURES • Ultra- low additive jitter: 50 fs rms • Buil t-in LDOs for high PSRR performance • Up to 10 LVPECL Outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS , CML, HCSL, LVCMOS) • Wid.


Silicon Laboratories SI53320

e frequency range: dc to 1250 MHz • Ou tput Enable option • Multiple configu ration options • Dual Bank option • 2:1 Input Mux operation • RoHS compl iant, Pb-free • Temperature range: 40 to +85 °C VDD Power Supply Filter ing 4 CLK0* CLK1* CLK_SEL 5 0 1 3 3 4 Outputs OEb 5 Outputs VDDOA OEAb 3 O utputs 3 Outputs OEBb VDDOB Si53323 Si 53320 Si53327/28 10 10 Outputs S.

Part

SI53320

Description

Low-Jitter LVPECL Fanout Clock Buffers



Feature


Si53320-28 Data Sheet Low-Jitter LVPECL Fanout Clock Buffers with up to 10 LVP ECL Outputs from Any-Format Input and W ide Frequency Range from DC up to 1250 MHz The Si53320–28 family of LVPECL f anout buffers is ideal for clock/data d istribution and redundant clocking appl ications. These devices feature typical ultra-low jitter characteristics of 50 fs and operate over.
Manufacture

Silicon Laboratories

Datasheet
Download SI53320 Datasheet




 SI53320
Si53320-28 Data Sheet
Low-Jitter LVPECL Fanout Clock Buffers with up to 10 LVPECL
Outputs from Any-Format Input and Wide Frequency Range from
DC up to 1250 MHz
The Si53320–28 family of LVPECL fanout buffers is ideal for clock/data distribution and
redundant clocking applications. These devices feature typical ultra-low jitter character-
istics of 50 fs and operate over a wide frequency range from dc to 725/1250 MHz. Built-
in LDOs deliver high PSRR performance and reduce the need for external components,
simplifying low-jitter clock distribution in noisy environments.
The Si53320–28 family is available in multiple configurations, with some versions offer-
ing a selectable input clock using a 2:1 input mux. Other features include independent
output enable and built-in format translation. These buffers can be paired with the
Si534x clocks and Si5xx oscillators to deliver end-to-end clock tree performance.
KEY FEATURES
• Ultra-low additive jitter: 50 fs rms
• Built-in LDOs for high PSRR performance
• Up to 10 LVPECL Outputs
• Any-format Inputs (LVPECL, Low-power
LVPECL, LVDS, CML, HCSL, LVCMOS)
• Wide frequency range: dc to 1250 MHz
• Output Enable option
• Multiple configuration options
• Dual Bank option
• 2:1 Input Mux operation
• RoHS compliant, Pb-free
• Temperature range: –40 to +85 °C
VDD
Power Supply Filtering
4
CLK0*
CLK1*
CLK_SEL
5
0
1
3
3
4 Outputs
OEb
5 Outputs
VDDOA
OEAb
3 Outputs
3 Outputs
OEBb
VDDOB
Si53323
Si53320
Si53327/28
10 10 Outputs Si53321/26
*Si53326/28 require Single-ended Inputs
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VDD
Power Supply Filtering
CLK 2 2 Outputs Si53322
VDD
Power Supply Filtering
CLK0 5 5 Outputs
Si53325
CLK1 5 5 Outputs
Rev. 1.2




 SI53320
1. Ordering Guide
Si53320-28 Data Sheet
Ordering Guide
Part Number
Si53320-B-GT
Si53321-B-GM
Si53321-B-GQ
Si53322-B-GM
Si53323-B-GM
Si53325-B-GM
Si53325-B-GQ
Si53326-B-GM
Si53327-B-GM
Si53328-B-GM
Table 1.1. Si5332x Ordering Guide
Input
2:1 selectable MUX
Any-format
2:1 selectable MUX
Any-format
2:1 selectable MUX
Any-format
1 bank / 1 Input
Any-format
2:1 selectable MUX
Any-format
2 banks / 2 Inputs
Any-format
2 banks / 2 Inputs
Any-format
2:1 selectable MUX
LVCMOS
2:1 selectable MUX
Any-format
2:1 selectable MUX
LVCMOS
LVPECL Output
1 bank / 5 Outputs
1 bank / 10 Outputs
1 bank / 10 Outputs
1 bank / 2 Outputs
1 bank / 4 Outputs
2 banks / 5 Outputs
2 banks / 5 Outputs
1 bank / 10 Outputs
2 banks / 3 Outputs
2 banks / 3 Outputs
Output Enable
Single
1 per bank
1 per bank
Frequency Range
dc to 725 MHz
dc to 1250 MHz
dc to 1250 MHz
dc to 1250 MHz
dc to 1250 MHz
dc to 1250 MHz
dc to 1250 MHz
dc to 200 MHz
dc to 1250 MHz
dc to 200 MHz
Package
20-TSSOP
32-QFN
5 x 5 mm
32-eLQFP
7 x 7 mm
16-QFN
3 x 3 mm
16-QFN
3 x 3 mm
32-QFN
5 x 5 mm
32-eLQFP
7 x 7 mm
32-QFN
5 x 5 mm
24-QFN
4 x 4 mm
24-QFN
4 x 4 mm
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Rev. 1.2 | 1




 SI53320
Si53320-28 Data Sheet
Functional Description
2. Functional Description
The Si53320-28 are a family of low-jitter, low-skew, fixed-format (LVPECL) buffers. All devices except the Si53326 and Si53328 have a
universal input that accepts most common differential or LVCMOS input signals. The Si53326 and Si53328 accept only single-ended
LVCMOS inputs. These devices are available in multiple configurations customized for the end application (refer to 1. Ordering Guide
for more details on configurations).
2.1 Universal, Any-Format Input Termination (Si53320/21/22/23/25/27)
The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, low-power LVPECL,
LVCMOS, LVDS, HCSL, and CML. The tables below summarize the various ac- and dc-coupling options supported by the device. For
the best high-speed performance, the use of differential formats is recommended. For both single-ended and differential input clocks,
the fastest possible slew rate is recommended since low slew rates can increase the noise floor and degrade jitter performance.
Though not required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats.
See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information.
Table 2.1. Clock Input Options
Clock Format
LVPECL/Low-power LVPECL
LVCMOS
LVDS
HCSL
CML
LVPECL/Low-power LVPECL
LVCMOS
LVDS
HCSL
CML
AC-Coupled
DC-Coupled
1.8 V
N/A
No
Yes
No
Yes
N/A
No
No
No
No
2.5/3.3 V
Yes
Yes
Yes
Yes (3.3 V)
Yes
Yes
Yes
Yes
Yes (3.3 V)
No
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Rev. 1.2 | 2



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