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Clock Buffers. SI53340 Datasheet

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Clock Buffers. SI53340 Datasheet






SI53340 Buffers. Datasheet pdf. Equivalent




SI53340 Buffers. Datasheet pdf. Equivalent





Part

SI53340

Description

Low-Jitter LVDS Fanout Clock Buffers



Feature


Si53340-45 Data Sheet Low-Jitter LVDS F anout Clock Buffers with up to 10 LVDS Outputs from Any-Format Input and Wide Frequency Range from dc up to 1250 MHz The Si53340-45 family of LVDS fanout bu ffers is ideal for clock/data distribut ion and redundant clocking applications . These devices feature typical ultra-l ow jitter of 50 fs and operate over a w ide frequency rang.
Manufacture

Silicon Laboratories

Datasheet
Download SI53340 Datasheet


Silicon Laboratories SI53340

SI53340; e from dc to 1250 MHz. Built-in LDOs del iver high PSRR performance and reduces the need for external components simpli fying low jitter clock distribution in noisy environments. They are available in multiple configurations and offer a selectable input clock using a 2:1 inpu t mux. Other features include independe nt output enable and built-in format tr anslation. These b.


Silicon Laboratories SI53340

uffers can be paired with the Si534x clo cks and Si5xx oscillators to deliver en d-to-end clock tree performance. KEY F EATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PS RR performance • Up to 10 LVDS Output s • Any-format Inputs (LVPECL, Low-Po wer LVPECL, LVDS, CML, HCSL, LVCMOS) Wide frequency range: dc to 1250 MHz • Output Enable option • Mul.


Silicon Laboratories SI53340

tiple configuration options • 2:1 Inpu t Mux • RoHS compliant, Pb-free • T emperature range: –40 to +85 °C CLK 0* CLK1* CLK_SEL VDD Power Supply Filt ering 4 03 3 1 4 Outputs Si53340/41 VDDOA OEAb 3 Outputs 3 Outputs OEBb VD DOB Si53342/43 10 10 Outputs Si53344/ 45 *Si53341/43/45 require Single-ended Inputs silabs.com | Smart. Connected. Energy-friendly. Rev. 1.2.

Part

SI53340

Description

Low-Jitter LVDS Fanout Clock Buffers



Feature


Si53340-45 Data Sheet Low-Jitter LVDS F anout Clock Buffers with up to 10 LVDS Outputs from Any-Format Input and Wide Frequency Range from dc up to 1250 MHz The Si53340-45 family of LVDS fanout bu ffers is ideal for clock/data distribut ion and redundant clocking applications . These devices feature typical ultra-l ow jitter of 50 fs and operate over a w ide frequency rang.
Manufacture

Silicon Laboratories

Datasheet
Download SI53340 Datasheet




 SI53340
Si53340-45 Data Sheet
Low-Jitter LVDS Fanout Clock Buffers with up to 10 LVDS Out-
puts from Any-Format Input and Wide Frequency Range from dc
up to 1250 MHz
The Si53340-45 family of LVDS fanout buffers is ideal for clock/data distribution and re-
dundant clocking applications. These devices feature typical ultra-low jitter of 50 fs and
operate over a wide frequency range from dc to 1250 MHz. Built-in LDOs deliver high
PSRR performance and reduces the need for external components simplifying low jitter
clock distribution in noisy environments.
They are available in multiple configurations and offer a selectable input clock using a
2:1 input mux. Other features include independent output enable and built-in format
translation. These buffers can be paired with the Si534x clocks and Si5xx oscillators to
deliver end-to-end clock tree performance.
KEY FEATURES
• Ultra-low additive jitter: 50 fs rms
• Built-in LDOs for high PSRR performance
• Up to 10 LVDS Outputs
• Any-format Inputs (LVPECL, Low-Power
LVPECL, LVDS, CML, HCSL, LVCMOS)
• Wide frequency range: dc to 1250 MHz
• Output Enable option
• Multiple configuration options
• 2:1 Input Mux
• RoHS compliant, Pb-free
• Temperature range: –40 to +85 °C
CLK0*
CLK1*
CLK_SEL
VDD
Power Supply
Filtering
4
03
3
1
4 Outputs Si53340/41
VDDOA
OEAb
3 Outputs
3 Outputs
OEBb
VDDOB
Si53342/43
10 10 Outputs Si53344/45
*Si53341/43/45 require Single-ended Inputs
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.2




 SI53340
1. Ordering Guide
Si53340-45 Data Sheet
Ordering Guide
Part Number
SI53340-B-GM
SI53341-B-GM
SI53342-B-GM
SI53343-B-GM
SI53344-B-GM
SI53345-B-GM
Table 1.1. Si5334x Ordering Guide
Input
2:1 selectable MUX
Any-format
2:1 selectable MUX
LVCMOS
2:1 selectable MUX
Any-format
2:1 selectable MUX
LVCMOS
2:1 selectable MUX
Any-format
2:1 selectable MUX
LVCMOS
LVDS Output
1 bank / 4 Outputs
1 bank / 4 Outputs
2 banks / 3 Outputs
2 banks / 3 Outputs
1 bank / 10 Outputs
1 bank / 10 Outputs
Output Enable (OE)
1 per bank
1 per bank
Frequency Range
dc to 1250 MHz
dc to 200 MHz
dc to 1250 MHz
dc to 200 MHz
dc to 1250 MHz
dc to 200 MHz
Package
16-QFN
3 x 3 mm
16-QFN
3 x 3 mm
24-QFN
4 x 4 mm
24-QFN
4 x 4 mm
32-QFN
5 x 5 mm
32-QFN
5 x 5 mm
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.2 | 1




 SI53340
Si53340-45 Data Sheet
Functional Description
2. Functional Description
The Si53340-45 are a family of low-jitter, low skew, fixed format (LVDS) buffers. The Si53340/42/44 have a universal input that accepts
most common differential or LVCMOS input signals, while the Si53341/43/45 accept only LVCMOS inputs. These devices are available
in multiple configurations customized for the end application (refer to 1. Ordering Guide for more details on configurations).
2.1 Universal, Any-Format Input Termination (Si53340/42/44)
The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, Low-power LVPECL, LVDS,
CML, HCSL, and LVCMOS. The tables below summarize the various ac- and dc-coupling options supported by the device. For the best
high-speed performance, the use of differential formats is recommended. For both single-ended and differential input clocks, the fastest
possible slew rate is recommended since low slew rates can increase the noise floor and degrade jitter performance. Though not re-
quired, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats. See “AN766:
Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information.
Table 2.1. Clock Input Options
Clock Format
LVPECL/Low-power LVPECL
LVCMOS
LVDS
HCSL
CML
LVPECL/Low-power LVPECL
LVCMOS
LVDS
HCSL
CML
AC-Coupled
DC-Coupled
1.8 V
N/A
No
Yes
No
Yes
N/A
No
No
No
No
2.5/3.3 V
Yes
Yes
Yes
Yes (3.3 V)
Yes
Yes
Yes
Yes
Yes (3.3 V)
No
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.2 | 2



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