SI53360

Si53360/61/62/65 Data Sheet Low-Jitter, LVCMOS Fanout Clock Buffers with up to 12 outputs and Frequency Range from dc to 200 MHz The Si53360/61/62/65 family of LVCMOS fanout buffers is ideal for clock/data distribution and redundant clocking applications. The family utilizes Silicon Labs advanced CMOS technology to fanout clocks from dc to 200 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. Built-in LDOs deliver high PSRR performance and eliminates the need for external components simplifying low jitter clock distribution in noisy environments. The CMOS buffers are available in multiple configurations with 8 outputs (Si53360/61/65), or dual banks of 6 outputs each (Si53362). These buffers can be paired with the Si534x clock generators and Si5xx oscillators to deliver end-to-end clock tree performance. KEY FEATURES Low additive jitter: 120 fs rms Built-in LDOs for high PSRR performance Up to 12 LVCMOS Outputs from LVCMOS inputs Frequency range: dc to 200 MHz Multiple configuration options Dual Bank option 2:1 Input MUX option RoHS compliant, Pb-free Temperature range: –40 to +85 °C VDD Power Supply Filtering CLK0 CLK1 CLK_SEL 0 1 8 6 6 VDDO (Si53361 only) OEA 8 Outputs Si53360/61 VDDOA OEA 6 Outputs 6 Outputs OEB VDDOB Si53362 VDD Power Supply Filtering CLK OE Si53365 8 8 Outputs silabs.com | Building a more connected world. Rev. 1.3 Table of Contents 1. Ordering Guide . . . . . . . . . . . . . . . ....