Document
SEMICONDUCTOR
M40T Series RRooHHSS
TRIACs, 40A Sunbberless
FEATURES
High current triac Low thermal resistance with clip bonding
Low thermal resistance insulation ceramic for insulated TO-3 package High commutation capability Packages are RoHS compliant
APPLICATIONS
Due to their clip assembly techinque, they provide a superior performance in surge current handling capabilities.
By using an internal ceramic pad, the M40T series provides voltage insulated tab (rated at 2500VRMS) complying with UL standards.
The snubberless concept offer suppression of RC network and it is suitable for applications such as :
Static relays Solid state switches Motor controls Light dimmers
Copy machines Microwave ovens Heater controls
T2 T1
G
MAIN FEATURES
SYMBOL IT(RMS)
VDRM/VRRM IGT(Q1)
VALUE 40
600 to 1200 10 to 50
UNIT A V mA
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RMS on-state current (full sine wave)
Non repetitive surge peak on-state current (full cycle, Tj initial = 25°C) I2t Value for fusing Critical rate of rise of on-state current IG = 2xlGT, tr≤100ns Peak gate current Peak gate power dissipation (tp = 20µs)
Average gate power dissipation
IT(RMS) ITSM I2t dI/dt IGM PGM PG(AV)
F =50 Hz F =60 Hz tp = 10 ms
F =100 Hz
Tp =20 µs Tj =125ºC Tj =125ºC
Storage temperature range Operating junction temperature range
Tstg Tj
TEST CONDITIONS Tc = 90ºC t = 20 ms t = 16.7 ms
VALUE 40 400 420 800
UNIT A
A A2s
Tj =125ºC 50 A/µs
Tj =125ºC
4 10 1 - 40 to + 150 - 40 to + 125
A W
ºC
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SEMICONDUCTOR
M40T Series RRooHHSS
ELECTRICAL CHARACTERISTICS (TJ= 25 ºC unless otherwise specified) SNUBBERLESS and Logic level (3 quadrants)
SYMBOL
TEST CONDITIONS
QUADRANT
IGT(1) VGT VGD IH(2)
VD = 12 V, RL = 33Ω
VD = VDRM, RL = 3.3KΩ Tj = 125°C IT = 500 mA
IL IG = 1.2 IGT
dV/dt(2) (dI/dt)c(2)
VD = 67% VDRM, gate open ,Tj = 125°C Without snubber, Tj = 125°C
I - II - III I - II - III I - II - III
I - III II
MAX. MIN. MAX. MAX. MIN.
Limits BW 50 1.3
0.2
60 80 150 1000 20
Unit mA V V mA mA V/µs A/ms
STATIC CHARACTERISTICS
SYMBOL VTM(2) Vt0(2) Rd(2)
IDRM IRRM
ITM = 60 A, tP = 380 µs Threshold voltage Dynamic resistance
VD = VDRM VR = VRRM
TEST CONDITIONS Tj = 25°C Tj = 125°C Tj = 125°C Tj = 25°C Tj = 125°C
Note 1: Minimum lGT is guaranted at 5% of lGT max. Note 2: For both polarities of A2 referenced to A1.
MAX. MAX. MAX.
MAX.
VALUE 1.55 0.85 10 10 5
UNIT V V mΩ µA mA
THERMAL RESISTANCE
SYMBOL Rth(j-c) Rth(j-a)
S = Copper surface under tab.
Junction to case (AC) Junction to ambient
VALUE 0.8 50
UNIT °C/W
PRODUCT SELECTOR
PART NUMBER M40TxxA
600 V V
VOLTAGE (x x) 800 V 1000 V
VV
1200 V V
SENSITIVITY 50 mA
TYPE Snubberless
PACKAGE TO-3
ORDERING INFORMATION
ORDERING TYPE
MARKING
M40TxxA
M40TxxA
Note : xx = voltage
PACKAGE TO-3
WEIGHT 23g
BASE Q,TY DELIVERY MODE 50 BOX
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SEMICONDUCTOR
M40T Series RRooHHSS
ORDERING INFORMATION SCHEME
Module type
M = TO-3 Fast-on package
Current
40 = 40A
Triac series
Voltage
60 = 600V 80 = 800V 100 = 1000V 120 = 1200V
Assembly type
A = Soldering Assembly
M 40 T 60 A
Fig.1 Maximum power dissipation versus on-state RMS current (full cycle)
P (W) 50
40
30
20
10
0 0
IT(RMS)(A)
180° α
α
5 10 15 20 25 30 35 40
Fig.2 On-state RMS current versus case temperature (full cycle)
IT(RMS) (A) 45
40
35 30
25 20
15 10
5 0
0 25
α=180°
Tc(°c) 50
75
100 125
Fig.3 Relative variation of thermal impedance versus pulse duration.
K=[Zth/Rth] 1E+00
Zth(j-c)
1E-01
Fig.4 On-state characteristics (maximum values).
ITM(A) 400 100 Tj=Tj max
1E-02
1E-03 1E-03
1E-02
1E-01
10 Tj=25°C
tp(s) 1E+00 1E+01 1E+02
1E+0.3
VTM(V)
Tj max. Vto = 0.85 V Rd = 10 mΩ
1
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
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SEMICONDUCTOR
M40T Series RRooHHSS
Fig.5 Surge peak on-state current versus number of cycles.
Fig.6 Non-repetitive surge peak on-state current for a sinusoidal pulse and corresponding value of l2t.
ITSM(A)
450
400
350 Non repetitive
300 Tj initial=25°C
250
200
150 Repetitive Tc=70°C
100
50 Number of cycles
0 1 10 100
t=20ms One cycle
ITSM(A),l2t(A2s) 10000
1000
dl/dt limitation 50A/µs
ITSM
Tj initial =25°C Pulse width tp <10 ms
I2t
1000
100 0.01
tp(ms) 0.10
1.00
10.00
Fig.7 Relative variation of gate trigger, holding and latching current versus junction temperature.
lGT,lH,lL[Tj] / lGT,lH,lL [Tj=25°C] 2.5
2.0 lGT
1.5
lH & lL 1.0
Typical values
0.5
Tj(°C)
0.0 -40 -20 0 20 40 60 80 100 120 140
Fig.8 Relative variation of critical rate of decrease of main current versus (dV/dt)c (typical values).
(dI/dt)c [(dV/dt)c] / specified (dI/dt)c 2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4 0.1
(dV/dt)c (V/µs) 1.0 10.0
100.0
Fig.9 Relative variation of critical rate of decrease of main current versus (dV/dt)c.
(dI/dt)c [Tj] / (dI/dt)c [Tj specified] 6
5 4
3
2
1 Tj(°C) 0
0 25 50 75 100 125
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SEMICONDUCTOR
Case Style
TO-3
M40T Series RRooHHSS
2-Ø4..