HY27SS08121A

HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Document Title 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory Revision History Revision No. 0.0 0.1 0.2 History Draft Date Remark Initial Draft. Sep. 2004 Preliminary 1) Correct part number ( change mode) - 2A -> 1A (sequential row read : disable -> enable) 2) Correct Table.5 & Table 12 - Correct Command Set - correct AC timing characteristics (tWP : 40 -> 25ns, tWH : 20 ->15ns) 3) Correct Summary description & page.7 - The cache feature is deleted in summary description. - Note.3 is deleted. (page.7) 4) Add System interface using CE don’t care (page. 38) 5) Change TSOP1, WSOP1,FBGA package dimension & figures. Oct. 22. 2004 Preliminary - Change TSOP1, WSOP1, FBGA package mechanical data - Change TSOP1, WSOP package figures 6) Correct TSOP1, WSOP1 Pin configuration - 38th NC pin has been changed Lockpre (figure 2,3) 7) Add Bad block Management 1) LOCKPRE is changed to PRE - Texts, Table and figures are changed. 2) Change Command set - Read A,B are changed to Read1. - Read C is changed to Read2. 3) Change AC, DC characterics - tRB, tCRY, tCEH and tOH are added. 4) Correct Program time (max) - before : 700us - after : 500us 5) Edit figures - Address names are changed. 6) Change FBGA Package Dimension - FD1 : 1.70(before) -> 0.90(after) Mar. 08. 2005 Preliminary Rev 1.1 / Fev. 2006 1 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND F...