Document
STM32F745xx STM32F746xx
ARM®-based Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 1MB Flash/320+16+ 4KB RAM, USB OTG HS/FS, ethernet, 18 TIMs, 3 ADCs, 25 com itf, cam & LCD
Datasheet - production data
Features
• Core: ARM® 32-bit Cortex®-M7 CPU with FPU, adaptive real-time accelerator (ART Accelerator™) and L1-cache: 4KB data cache and 4KB instruction cache, allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions.
• Memories – Up to 1MB of Flash memory – 1024 bytes of OTP memory – SRAM: 320KB (including 64KB of data TCM RAM for critical real-time data) + 16KB of instruction TCM RAM (for critical real-time routines) + 4KB of backup SRAM (available in the lowest power modes) – Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
• Dual mode Quad-SPI • LCD parallel interface, 8080/6800 modes • LCD-TFT controller up to XGA resolution with
dedicated Chrom-ART Accelerator™ for enhanced graphic content creation (DMA2D)
• Clock, reset and supply management – 1.7 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – Dedicated USB power – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration
• Low-power
– Sleep, Stop and Standby modes
–
VreBgAisTtseurspp+ly4KfoBr
RTC, 32×32 bit backup SRAM
backup
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• Up to 18 timers: up to thirteen 16-bit (1x lowpower 16-bit timer available in Stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer
&"'!
LQFP100 (14x14 mm)
LQFP144 (20x20 mm) LQFP176 (24x24 mm) LQFP208 (28x28 mm)
UFBGA176 (10x10 mm) TFBGA216 (13x13 mm) TFBGA100 (8x8 mm)
WLCSP143 (4.5x5.8 mm)
• General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
• Debug mode
– SWD & JTAG interfaces – Cortex®-M7 Trace Macrocell™
• Up to 168 I/O ports with interrupt capability
– Up to 164 fast I/Os up to 108 MHz
– Up to 166 5 V-tolerant I/Os
• Up to 25 communication interfaces – Up to 4× I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs/4 UARTs (27 Mbit/s, ISO7816 interface, LIN, IrDA, modem control)
–
Umpuxtoed6sSimPpIsle(xupI2tSo
50 for
Mbit/s), 3 with audio class
accuracy via internal audio PLL or external
clock
– 2 x SAIs (serial audio interface)
– 2 × CANs (2.0B active) and SDMMC interface
– SPDIFRX interface
– HDMI-CEC
• Advanced connectivity
– USB 2.0 full-speed device/host/OTG controller with on-chip PHY
– USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI
– 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII
• 8- to 14-bit parallel camera interface up to 54 Mbyte/s
• True random number generator
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID
Table 1. Device summary
Reference
Part number
STM32F745xx STM32F746xx
STM32F745IE, STM32F745VE, STM32F745VG, STM32F745ZE, STM32F745ZG, STM32F745IG STM32F746BE, STM32F746BG, STM32F746IE, STM32F746IG, STM32F746NE, STM32F746NG, STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG
February 2016
This is information on a product in full production.
DocID027590 Rev 4
1/227
www.st.com
Contents
Contents
STM32F745xx STM32F746xx
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Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1 ARM® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 18 2.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6 AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.8 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.9 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.10 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.11 Chrom-ART Accelerator™ (DMA.