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STP110N8F7 Dataheets PDF



Part Number STP110N8F7
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description N-channel Power MOSFET
Datasheet STP110N8F7 DatasheetSTP110N8F7 Datasheet (PDF)

STP110N8F7 N-channel 80 V, 6.4 mΩ typ., 80 A, STripFET™ F7 Power MOSFET in a TO-220 package Datasheet - production data Figure 1: Internal schematic diagram Features Order code STP110N8F7 VDS 80 V RDS(on)max 7.5 mΩ ID 80 A PTOT 170 W  Among the lowest RDS(on) on the market  Excellent figure of merit (FoM)  Low Crss/Ciss ratio for EMI immunity  High avalanche ruggedness Applications  Switching applications Description This N-channel Power MOSFET utilizes STripFET™ F7 technology with.

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STP110N8F7 N-channel 80 V, 6.4 mΩ typ., 80 A, STripFET™ F7 Power MOSFET in a TO-220 package Datasheet - production data Figure 1: Internal schematic diagram Features Order code STP110N8F7 VDS 80 V RDS(on)max 7.5 mΩ ID 80 A PTOT 170 W  Among the lowest RDS(on) on the market  Excellent figure of merit (FoM)  Low Crss/Ciss ratio for EMI immunity  High avalanche ruggedness Applications  Switching applications Description This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. Order code STP110N8F7 Table 1: Device summary Marking Package 110N8F7 TO-220 Packaging Tube November 2015 DocID027154 Rev 2 This is information on a product in full production. 1/13 www.st.com Contents Contents STP110N8F7 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves)...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package mechanical data ............................................................... 9 4.1 TO-220 package mechanical data .................................................. 10 5 Revision history ............................................................................ 12 2/13 DocID027154 Rev 2 STP110N8F7 1 Electrical ratings Electrical ratings Symbol VDS VGS ID ID IDM(2) PTOT EAS(3) TJ Tstg Table 2: Absolute maximum ratings Parameter Drain-source voltage Gate-source voltage Drain current (continuous) at TC = 25 °C Drain current (continuous) at TC = 100 °C Drain current (pulsed) Total dissipation at TC = 25 °C Single pulse avalanche energy Operating junction temperature Storage temperature Notes: (1)Limited by package (2)Pulse width is limited by safe operating area (3)Starting Tj = 25°C, Id = 25 A, Vdd = 40 V Value 80 ±20 80 (1) 76 320 170 220 -55 to 175 Unit V V A A A W mJ °C °C Symbol Rthj-case Rthj-amb Table 3: Thermal data Parameter Thermal resistance junction-case max Thermal resistance junction-ambient max Value 0.88 62.5 Unit °C/W °C/W DocID027154 Rev 2 3/13 Electrical characteristics STP110N8F7 2 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: On /off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage VGS = 0, ID = 250 µA Zero gate voltage IDSS drain current VGS = 0, VDS = 80 V VGS = 0, VDS = 80 V, TC = 125 °C Gate-body leakage IGSS current VDS = 0, VGS = ± 20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 40 A Min. 80 Typ. Max. Unit V 1 µA 10 µA ±100 nA 2.5 4.5 V 6.4 7.5 mΩ Symbol Ciss Coss Crss Qg Qgs Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Qgd Gate-drain charge Table 5: Dynamic Test conditions VGS = 0, VDS = 40 V, f = 1 MHz VDD = 40 V, ID = 80 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior" ) Min. - - - - Typ. 3435 653 57 46.8 23.4 11.2 Max. - Unit pF pF - pF - nC - nC - nC Symbol td(on) tr td(off) Parameter Turn-on delay time Rise time Turn-off delay time tf Fall time Table 6: Switching times Test conditions VDD = 40 V, ID = 40 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform" ) Min. - - Typ. 49 95 60 32 Max. - Unit ns ns ns - ns 4/13 DocID027154 Rev 2 STP110N8F7 Symbol VSD(1) trr Qrr IRRM Parameter Table 7: Source drain diode Test conditions Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current VGS = 0, ISD = 80 A ISD = 80 A, di/dt = 100 A/µs VDD = 60 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") Electrical characteristics Min. - Typ. 48.6 58.6 Max. 1.2 Unit V ns nC - 2.4 A Notes: (1)Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID027154 Rev 2 5/13 Electrical characteristics 2.2 Electrical characteristics (curves) Figure 2: Safe operating area STP110N8F7 Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/13 DocID027154 Rev 2 STP110N8F7 Figure 8: Capacitance variations Electrical characteristics Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics DocID027154 Rev 2 7/13 Test circuits 3 Test circuits Figure 13: Test circuit for resistive load.


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