HD74HC107

HD74HC107 Dual J-K Flip-Flops (with Clear) REJ03D0559-0200 (Previous ADE-205-432) Rev.2.00 Oct 06, 2005 Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and accomplished by a low level on the input. Features High Speed Operation: tpd (Clock to Q) = 19 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74HC107P DILP-14 pin PRDP0014AB-B (DP-14AV) P HD74HC107FPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP HD74HC107RPEL SOP-14 pin (JEDEC) PRSP0014DE-A (FP-14DNV) RP Note: Please consult the sales office for the above package availability. Taping Abbreviation (Quantity) — EL (2,000 pcs/reel) EL (2,500 pcs/reel) Function Table Inputs Outputs Clear Clock J K Q Q L XXX LH H LL No change H LHLH H HLHL H HH Toggle HLXX No change HHXX No change H XX No change H : High level L : Low level X : Irrelevant Rev.2.00, Oct 06, 2005 page 1 of 7 HD74HC107 Pin Arrangement Logic Diagram (1/2) CLR J K 1J 1 1Q 2 1Q 3 1K 4 2Q 5 2Q 6 GND 7 Q CLR J CK Q K QK CK Q CLR J (Top View) 14 Vcc 13 1CLR 12 1CK 11 2K...