HD74HC273

HD74HC273 Octal D-type Flip-Flops (with Clear) REJ03D0604-0300 Rev.3.00 Mar 25, 2009 Description This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state. Features High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name Package Type Package Code (Previous Code) HD74HC273P DILP-20 pin PRDP0020AC-B (DP-20NEV) HD74HC273FPEL SOP-20 pin (JEITA) PRSP0020DD-B (FP-20DAV) HD74HC273RPEL SOP-20 pin (JEDEC) PRSP0020DC-A (FP-20DBV) HD74HC273TELL TSSOP-20 pin PTSP0020JB-A (TTP-20DAV) Note: Please consult the sales office for the above package availability. Package Abbreviation P FP RP T Taping Abbreviation (Quantity) — EL (2,000 pcs/reel) EL (1,000 pcs/reel) ELL (2,000 pcs/reel) Function Table Note Inputs Clear Clock LX H H HL H 1. H: high level, L: low level, X: irrelevant D X H L X X Output Q L H L No change No change REJ03D0604-0300 Rev.3.00 Mar 25, 2009 Page 1 of 7 HD74HC273 Pin Arrangement Logic Diagram Clear 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9 GND 10 Q Clear D CK D CK Clear Q Q Clear D CK D...