HD74HC595

HD74HC595 8-bit Shift Register/Latch (with 3-state outputs) REJ03D0634-0200 (Previous ADE-205-514) Rev.2.00 Mar 30, 2006 Description This device each contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading. Both the shift register and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register state will always be one clock pulse ahead of the storage register. Features High Speed Operation: tpd (RCK to Q) = 17 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads (QA to QH outputs) Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74HC595P DILP-16 pin PRDP0016AE-B (DP-16FV) P HD74HC595FPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP Note: Please consult the sales office for the above package availability. Taping Abbreviation (Quantity) — EL (2,000 pcs/reel) Function Table RCK X X X SCK X X X Inputs SCLR X L H H G Function H QA to QH high impedance X Shift register cleared QH’ = L X Shift register clocked Qn = Qn – 1...