STU40N01

Gre Pro STU/D40N01 Sa mHop Microelectronics C orp. N-Channel Logic Level Enhancement Mode Field Effect Transistor Ver 1.0 PRODUCT SUMMARY VDSS ID RDS(ON) (mΩ) Typ 100V 40A 18 @ VGS=10V FEATURES Super high dense cell design for low RDS(ON). Rugged and reliable. TO-252 and TO-251 Package. G S STU SERIES TO - 252AA( D- PAK ) G DS STD SERIES TO - 251( I - PAK ) ABSOLUTE MAXIMUM RATINGS (TC=25°C unless otherwise noted) Symbol Parameter VDS Drain-Source Voltage VGS Gate-Source Voltage ID Drain Current-Continuous TC=25°C TC=70°C IDM -Pulsed a PD Maximum Power Dissipation TC=25°C TC=70°C TJ, TSTG Operating Junction and Storage Temperature Range THERMAL CHARACTERISTICS R JC Thermal Resistance, Junction-to-Case R JA Thermal Resistance, Junction-to-Ambient Limit 100 ±20 40 33.5 117 75 52.5 -55 to 175 2 50 Units V V A A A W W °C °C/W °C/W Details are subject to change without notice. 1 Jul,05,2012 www.samhop.com.tw STU/D40N01 Ver 1.0 ELECTRICAL CHARACTERISTICS (TC=25°C unless otherwise noted) Symbol Parameter Conditions Min OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate-Body Leakage Current VGS=0V , ID=250uA VDS=80V , VGS=0V VGS= ±20V , VDS=0V 100 ON CHARACTERISTICS VGS(th) Gate Threshold Voltage RDS(ON) gFS Drain-Source On-State Resistance Forward Transconductance DYNAMIC CHARACTERISTICS b CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance SWITCHING...