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VS-VSK.230..PbF Series
Vishay Semiconductors
SCR/SCR and SCR/Diode (MAGN-A-PAK Power Modules), 230 A
MAGN-A-PAK
PRODUCT SUMMARY
IT(AV) Type Package Circuit
230 A Modules - Thyristor, Standard
MAGN-A-PAK Two SCRs doubler circuit
FEATURES • High voltage
• Electrically isolated base plate
• 3500 VRMS isolating voltage • Industrial standard package
• Simplified mechanical designs, rapid assembly
• High surge capability
• Large creepage distances
• UL approved file E78996
• Designed and qualified for industrial level
• Material categorization: for definitions of compliance please see www.vishay.com/doc?99912
DESCRIPTION This new VSK series of MAGN-A-PAK modules uses high voltage power thyristor/thyristor and thyristor/diode in seven basic configurations. The semiconductors are electrically isolated from the metal base, allowing common heatsinks and compact assemblies to be built. They can be interconnected to form single phase or three phase bridges or as AC-switches when modules are connected in anti-parallel mode. These modules are intended for general purpose applications such as battery chargers, welders, motor drives, UPS, etc.
MAJOR RATINGS AND CHARACTERISTICS
SYMBOL
CHARACTERISTICS
IT(AV) IT(RMS)
ITSM
85 °C
50 Hz 60 Hz
50 Hz I2t
60 Hz
I2√t
VDRM/VRRM TJ
Range
ELECTRICAL SPECIFICATIONS
VOLTAGE RATINGS
VOLTAGE TYPE NUMBER
CODE
VS-VSK.230-
08 12 16 18 20
VRRM/VDRM, MAXIMUM REPETITIVE PEAK REVERSE AND OFF-STATE
BLOCKING VOLTAGE V
800
1200
1600
1800
2000
VALUES 230 510 7500 7850 280 260 280
800 to 2000 -40 to 130
VRSM, MAXIMUM NON-REPETITIVE PEAK
REVERSE VOLTAGE V
900 1300 1700 1900 2100
UNITS
A
kA2s kA2√s
V °C
IRRM/IDRM AT 130 °C MAXIMUM
mA
50
Revision: 17-Jul-14
1 Document Number: 93053
For technical questions within your region:
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com
VS-VSK.230..PbF Series
Vishay Semiconductors
ON-STATE CONDUCTION
PARAMETER Maximum average on-state current at case temperature Maximum RMS on-state current
Maximum peak, one-cycle on-state non-repetitive, surge current
SYMBOL IT(AV) IT(RMS)
ITSM
Maximum I2t for fusing
I2t
Maximum I2√t for fusing Low level value or threshold voltage High level value of threshold voltage Low level value on-state slope resistance High level value on-state slope resistance
Maximum on-state voltage drop
Maximum holding current
Maximum latching current
I2√t VT(TO)1 VT(TO)2
rt1 rt2
VTM
IH
IL
TEST CONDITIONS
180° conduction, half sine wave
As AC switch
t = 10 ms
No voltage
t = 8.3 ms
reapplied
t = 10 ms t = 8.3 ms
100 % VRRM reapplied
Sinusoidal half wave,
t = 10 ms
No voltage
initial
t = 8.3 ms
reapplied
TJ = TJ maximum
t = 10 ms t = 8.3 ms
100 % VRRM reapplied
t = 0.1 ms to 10 ms, no voltage reapplied
(16.7 % x π x IT(AV) < I < π x IT(AV)), TJ = TJ maximum (I > π x IT(AV)), TJ = TJ maximum (16.7 % x π x IT(AV) < I < π x IT(AV)), TJ = TJ maximum (I > π x IT(AV)), TJ = TJ maximum ITM = π x IT(AV), TJ = TJ maximum, 180° conduction, average power = VT(TO) x IT(AV) + rf x (IT(RMS))2 Anode supply = 12 V, initial IT = 30 A, TJ = 25 °C Anode supply = 12 V, resistive load = 1 Ω,
gate pulse: 10 V, 100 μs, TJ = 25 °C
VALUES 230 85 510 7500 7850 6300 6600 280 256 198 181 2800 1.03 1.07 0.77 0.73
1.59
500
1000
UNITS A °C
A
kA2s kA2√s
V mΩ
V mA
SWITCHING
PARAMETER Typical delay time Typical rise time
Typical turn-off time
SYMBOL td tr
tq
TEST CONDITIONS
TJ = 25 °C, gate current = 1 A dIg/dt = 1 A/μs Vd = 0.67 % VDRM ITM = 300 A; dI/dt = 15 A/μs; TJ = TJ maximum; VR = 50 V; dV/dt = 20 V/μs; gate 0 V, 100 Ω
VALUES 1.0 2.0
50 to 150
UNITS μs
BLOCKING
PARAMETER Maximum peak reverse and off-state leakage current RMS insulation voltage Critical rate of rise of off-state voltage
SYMBOL
IRRM, IDRM VINS dV/dt
TEST CONDITIONS
TJ = TJ maximum 50 Hz, circuit to base, all terminals shorted, 25 °C, 1 s TJ = TJ maximum, exponential to 67 % rated VDRM
VALUES
50 3000 1000
UNITS
mA V V/μs
TRIGGERING
PARAMETER Maximum peak gate power Maximum average gate power Maximum peak gate current Maximum peak negative gate voltage
SYMBOL
PGM PG(AV) + IGM - VGT
Maximum required DC gate voltage to trigger VGT
Maximum required DC gate current to trigger
Maximum gate voltage that will not trigger Maximum gate current that willnot trigger Maximum rate of rise of turned-on current
IGT
VGD IGD dI/dt
TEST CONDITIONS
tp ≤ 5 ms, TJ = TJ maximum
f = 50 Hz, TJ = TJ maximum tp ≤ 5 ms, TJ = TJ maximum tp ≤ 5 ms, TJ = TJ maximum
TJ = - 40 °C TJ = 25 °C TJ = TJ maximum
Anode supply = 12 V, resistive load; Ra = 1 Ω
TJ = - 40 °C TJ = 25 °C TJ = TJ maximum
Anode supply = 12 V, resistive load; Ra = 1 Ω
TJ = TJ maximum, rated VDRM applied
TJ = TJ maximum, rated VDRM applied
TJ = TJ maximum, ITM = 400 A, rated VDRM .