Document
COP8SG Family, 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
January 2000
COP8SG Family 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART
General Description
The COP8SGx5 Family ROM based microcontrollers are highly integrated COP8™ Feature core devices with 8k to 32k memory and advanced features including Analog comparators, and zero external components. These single-chip CMOS devices are suited for more complex applications requiring a full featured controller with larger memory, low EMI, two comparators, and a full-duplex USART. COP8SGx7 devices are 100% form-fit-function compatible 8k or 32k OTP (One Time Programmable) versions for use in production or development. Erasable windowed versions are available for use with a range of COP8 software and hardware development tools. Family features include an 8-bit memory mapped architecture, 15 MHz CKI with 0.67 µs instruction cycle, 14 interrupts, three multi-function 16-bit timer/counters with PWM, full duplex USART, MICROWIRE/PLUS™, two analog comparators, two power saving HALT/IDLE modes, MIWU, idle timer, on-chip R/C oscillator, high current outputs, user selectable options (WATCHDOG™, 4 clock/oscillator modes, power-on-reset), 2.7V to 5.5V operation, program code security, and 28/40/44 pin packages. Devices included in this datasheet are:
Device COP8SGE5 COP8SGG5 COP8SGH5 COP8SGK5 COP8SGR5 COP8SGE7 COP8SGR7 COP8SGR7-Q3
Memory (bytes) 8k ROM 16k ROM 20k ROM 24k ROM 32k ROM 8k OTP EPROM 32k OTP EPROM 32k EPROM
RAM (bytes) 256 512 512 512 512 256 512 512
I/O Pins 24/36/40 24/36/40 24/36/40 24/36/40 24/36/40 24/36/40 24/36/40 24/36/40
Packages 28 DIP/SOIC, 40 DIP, 44 PLCC/QFP 28 DIP/SOIC, 40 DIP, 44 PLCC/QFP 28 DIP/SOIC, 40 DIP, 44 PLCC/QFP 28 DIP/SOIC, 40 DIP, 44 PLCC/QFP 28 DIP/SOIC, 40 DIP, 44 PLCC/QFP 28 DIP/SOIC, 40 DIP, 44 PLCC/QFP 28 DIP/SOIC, 40 DIP, 44 PLCC/QFP 28 DIP/SOIC, 40 DIP, 44 PLCC/QFP
Temperature -40 to +85˚C, -40 to +125˚C -40 to +85˚C, -40 to +125˚C -40 to +85˚C, -40 to +125˚C -40 to +85˚C, -40 to +125˚C -40 to +85˚C, -40 to +125˚C -40 to +85˚C, -40 to +125˚C -40 to +85˚C, -40 to +125˚C Room Temp.
Key Features
n n n n Low cost 8-bit microcontroller Quiet Design (low radiated emissions) Multi-Input Wakeup pins with optional interrupts (8 pins) Mask selectable clock options — Crystal oscillator — Crystal oscillator option with on-chip bias resistor — External oscillator — Internal R/C oscillator Internal Power-On-Reset — user selectable WATCHDOG and Clock Monitor Logic — user selectable Eight high current outputs 256 or 512 bytes on-board RAM 8k to 32k ROM or OTP EPROM with security feature
CPU Features
n Versatile easy to use instruction set n 0.67 µs instruction cycle time n Fourteen multi-source vectored interrupts servicing — External interrupt / Timers T0 — T3 — MICROWIRE/PLUS Serial Interface — Multi-Input Wake Up — Software Trap — USART (2; 1 receive and 1 transmit) — Default VIS (default interrupt) n 8-bit Stack Pointer SP (stack in RAM) n Two 8-bit Register Indirect Data Memory Pointers n True bit manipulation n BCD arithmetic instructions
n n n n n
COP8™, MICROWIRE/PLUS™, and WATCHDOG™ are trademarks of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. iceMASTER ® is a registered trademark of MetaLink Corporation.
© 2000 National Semiconductor Corporation
DS101317
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COP8SG Family
CPU Features
(Continued)
Peripheral Features
n Multi-Input Wakeup Logic n Three 16-bit timers (T1 — T3), each with two 16-bit registers supporting: — Processor Independent PWM mode — External Event Counter mode — Input Capture mode n Idle Timer (T0) n MICROWIRE/PLUS Serial Interface (SPI Compatible) n Full Duplex USART n Two Analog Comparators
n Schmitt trigger inputs on ports G and L n Eight high current outputs n Packages: 28 SO with 24 I/O pins, 40 DIP with 36 I/O pins, 44 PLCC and PQFP with 40 I/O pins
Fully Static CMOS Design
n Low current drain (typically < 4 µA) n Two power saving modes: HALT and IDLE
Temperature Range
n −40˚C to +85˚C, −40˚C to +125˚C
Development Support
n Windowed packages for DIP and PLCC n Real time emulation and full program debug offered by MetaLink Development System
I/O Features
n Software selectable I/O options (TRI-STATE ® Output,Push-Pull Output, Weak Pull-Up Input, and High Impedance Input)
Block Diagram
DS101317-44
FIGURE 1. COP8SGx Block Diagram
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COP8SG Family
1.0 Device Description
1.1 ARCHITECTURE The COP8 family is based on a modified Harvard architecture, which allows data tables to be accessed directly from program memory. This is very important with modern microcontroller-based applications, since program memory is usually ROM or EPROM, while data memory is usually RAM. Consequently data tables need to be contained in non-volatile memory, so they are not lost when the microcontroller is powered d.