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ST92F124R9 Dataheets PDF



Part Number ST92F124R9
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description 8/16-bit single voltage Flash MCU
Datasheet ST92F124R9 DatasheetST92F124R9 Datasheet (PDF)

ST92F124xx/ST92F150Cxx/ ST92F150JDV1/ST92F250CV2 8/16-bit single voltage Flash MCU family with RAM, E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD Datasheet − production data Features ■ Memories – Internal memory: Single Voltage Flash up to 256 Kbytes, RAM up to 8 Kbytes, 1 Kbyte E3 TM (Emulated EEPROM) – In-Application Programming (IAP) – 224 general purpose registers (register file) available as RAM, accumulators or index pointers ■ Clock, reset and supply management – Register-oriented 8.

  ST92F124R9   ST92F124R9


Document
ST92F124xx/ST92F150Cxx/ ST92F150JDV1/ST92F250CV2 8/16-bit single voltage Flash MCU family with RAM, E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD Datasheet − production data Features ■ Memories – Internal memory: Single Voltage Flash up to 256 Kbytes, RAM up to 8 Kbytes, 1 Kbyte E3 TM (Emulated EEPROM) – In-Application Programming (IAP) – 224 general purpose registers (register file) available as RAM, accumulators or index pointers ■ Clock, reset and supply management – Register-oriented 8/16 bit CORE with RUN, WFI, SLOW, HALT and STOP modes – 0-24 MHz Operation (Int. Clock), 4.5-5.5 V range – PLL Clock Generator (3-5 MHz crystal) – Minimum instruction time: 83 ns (24 MHz int. clock) ■ Up to 80 I/O pins ■ Interrupt management – 4 external fast interrupts + 1 NMI – Up to 16 pins programmable as wake-up or additional external interrupt with multi-level interrupt handler ■ DMA controller for reduced processor overhead ■ Timers – 16-bit Timer with 8-bit Prescaler, and Watchdog Timer (activated by software or by hardware) – 16-bit Standard Timer that can be used to generate a time base independent of PLL Clock Generator – Two 16-bit independent Extended Function Timers (EFTs) with Prescaler, up to two Input Captures and up to two Output Compares – Two 16-bit Multifunction Timers, with Prescaler, up to two Input Captures and up to two Output Compares ■ Communication interfaces – Serial Peripheral Interface (SPI) with selectable Master/Slave mode LQFP64 14x14 PQFP100 14x20 LQFP100 14x14 – One Multiprotocol Serial Communications Interface with asynchronous and synchronous capabilities – One asynchronous Serial Communications Interface with 13-bit LIN Synch Break generation capability – J1850 Byte Level Protocol Decoder (JBLPD) – Up to two full I²C multiple Master/Slave Interfaces supporting Access Bus – Up to two CAN 2.0B Active interfaces ■ Analog peripheral (low current coupling) – 10-bit A/D Converter with up to 16 robust input channels ■ Development tools – Free High performance development environment (IDE) based on Visual Debugger, Assembler, Linker, and C-Compiler; Real Time Operating System (OSEK OS, CMX) and CAN drivers – Hardware emulator and Flash programming board for development and ISP Flasher for production Table 1. Device summary Reference Part number ST92F124xx ST92F150Cxx ST92F150JDxx ST92F250Cxx ST92F124R1, ST92F124R9, ST92F124V1 ST92F150CR1, ST92F150CR9, ST92F150CV1, ST92F150CV9 ST92F150JDV1 ST92F250CV2 July 2012 This is information on a product in full production. Doc ID 8848 Rev 7 1/523 www.st.com 1 Contents Contents ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2 1 2 3 4 5 6 2/523 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.1 I/O port alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.2 Termination of unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1 Alternate functions for I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.1 Core architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.2 Memory spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.2.1 6.2.2 Register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 System registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 Central interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Flag register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Register pointing techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Paged registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Stack pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.5 Memory management unit . . . . . . . .


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