RNA52A10TH5

Data Sheet RNA52A10T Dual CMOS system–RESET IC R03DS0078EJ0200 Rev.2.00 Dec 19, 2015 Description The RNA52A10T incorporates two reset circuits, one with and one without a delay function, allowing the generation of separate reset signals for a microprocessor and associated system circuits. The detection voltage of each reset circuit is determined by the value of an external resistor, and the internal reference voltage is 1.0 V. The CMOS process for the RNA52A10T means that the device draws only 1.1 μA (typ.). The reset cancellation delay time is set with a high degree of accuracy by the values of a capacitor and resistor connected with the CD pin. The MR (manual reset) input pin is provided for the reset circuit with the delay function, and the reset signal is output in response to a high level on the MR input pin. The MR pin is pulled down by a 2-MΩ internal resistor. Output pins Vo1 and Vo2 are open drain. Features Two CMOS reset circuits, one with and one without the delay function Reference voltage: 1.0 V Reference voltage accuracy: ± 50 mV Reference voltage hysteresis: 6% (typ.) Low current consumption: 1.1 μA (typ.) Delay time set by an external CR circuit Manual reset input Open-drain output TSSOP-8 (8-pin) package Operating temperature range: – 40 to 85°C Ordering Information Part Name RNA52A10TH5 Package Type TSSOP-8 pin Package Code PTSP0008JC-B Package Abbreviation T Taping Abbreviation (Quantity) H (3,000 pcs / Reel) Surface Treatmen...