Document
CYStech Electronics Corp.
Spec. No. : C987J3 Issued Date : 2015.02.03 Revised Date : Page No. : 1/9
N -Channel Enhancement Mode Power MOSFET
MTB080N15J3 BVDSS
150V
ID @VGS=10V, TC=25°C
18A
RDS(ON)@VGS=10V, ID=10A 82.3mΩ(typ)
RDS(ON)@VGS=4.5V, ID=10A 85.8mΩ(typ)
Features
• Low Gate Charge • Simple Drive Requirement • Pb-free lead plating and halogen-free package
Equivalent Circuit
MTB080N15J3
Outline
TO-252(DPAK)
G:Gate D:Drain S:Source
G DS
Ordering Information
Device MTB080N15J3-0-T3-G
Package
TO-252 (Pb-free lead plating and halogen-free package)
Shipping 2500 pcs / Tape & Reel
Environment friendly grade : S for RoHS compliant products, G for RoHS compliant and green compound products Packing spec, T3 : 2500 pcs / tape & reel, 13” reel
Product rank, zero for no rank products
Product name
MTB080N15J3
CYStek Product Specification
CYStech Electronics Corp.
Absolute Maximum Ratings (TC=25°C, unless otherwise noted)
Parameter
Drain-Source Voltage Gate-Source Voltage Continuous Drain Current @ TC=25°C, VGS=10V Continuous Drain Current @ TC=100°C, VGS=10V Continuous Drain Current @ TA=25°C, VGS=10V Continuous Drain Current @ TA=100°C, VGS=10V Continuous Drain Current @ TA=25°C, VGS=10V Continuous Drain Current @ TA=100°C, VGS=10V Pulsed Drain Current *1 Avalanche Current Avalanche Energy @ L=6mH, ID=6.3A, RG=25Ω Total Power Dissipation @TC=25℃ Total Power Dissipation @TC=100℃ Total Power Dissipation @TA=25℃ Total Power Dissipation @TA=100℃ Total Power Dissipation @TA=25℃ Total Power Dissipation @TA=100℃ Operating Junction and Storage Temperature Range
Symbol
VDS VGS
ID
*2
*2 IDSM
*3 *3
IDM IAS EAS
PD
*2
*2 PDSM
*3 *3
Tj, Tstg
Spec. No. : C987J3 Issued Date : 2015.02.03 Revised Date : Page No. : 2/9
Limits
150 ±20 18.0 12.7 3.2 2.0 2.6 1.6 72 6.3 119 83 42 2.5 1.0 1.7 0.7 -55~+175
Unit
V
A
mJ W °C
Thermal Data
Parameter
Symbol
Thermal Resistance, Junction-to-case, max
Rth,j-c
Thermal Resistance, Junction-to-ambient, max Thermal Resistance, Junction-to-ambient, max
*2 *3
Rth,j-a
Value 2 50 75
Unit °C/W
Note : *1. Pulse width limited by maximum junction temperature
*2. When the device is mounted on 1 in²FR-4 board with 2 oz. copper. *3. When the device is on the minimum pad size recommended. *4. The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful
in setting the upper dissipation limit for cases where additional heatsinking is used. *5. The power dissipation PDSM is based on RθJA and the maximum allowed junction temperature of 150°C. The value
in any given application depends on the user’s specific board design, and the maximum temperature of 175°C may be used if the PCB allows it.
Characteristics (Tc=25°C, unless otherwise specified)
Symbol
Min. Typ. Max. Unit Test Conditions
Static
BVDSS
150 -
- V VGS=0V, ID=250μA
∆BVDSS/∆Tj - 0.15 - V/°C Reference to 25°C, ID=250μA
VGS(th)
1.0 - 2.5 V VDS =VGS, ID=250μA
GFS *1
-
18
-
S VDS =10V, ID=10A
I.