R5F117BA

RL78/I1D RENESAS MCU 1. OUTLINE 1.1 Features Ultra-low power consumption technology VDD = 1.6 V to 3.6 V HALT mode STOP mode SNOOZE mode RL78 CPU core CISC architecture with 3-stage pipeline Minimum instruction execution time: Can be changed from high speed (0.04167 μs: @ 24 MHz operation with high-speed on-chip oscillator) to ultra-low speed (66.6 μs: @ 15 kHz operation with low-speed on-chip oscillator clock) Multiply/divide/multiply & accumulate instructions are supported. Address space: 1 MB General-purpose registers: (8-bit register × 8) × 4 banks On-chip RAM: 0.7 to 3 KB Code flash memory Code flash memory: 8 to 32 KB Block size: 1 KB Prohibition of block erase and rewriting (security function) On-chip debug function Self-programming (with boot swap function/flash shield window function) Data flash memory Data flash memory: 2 KB Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory. Number of rewrites: 1,000,000 times (TYP.) Voltage of rewrites: VDD = 1.8 to 3.6 V High-speed on-chip oscillator Select from 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz High accuracy: ±1.0% (VDD = 1.8 to 3.6 V, TA = -20 to +85°C) Middle-speed on-chip oscillator Selectable from 4 MHz, 2 MHz, and 1 MHz. Operating ambient temperature TA = -40 to +105°C (G: Industrial applications) Power management and reset function On-chip power-on-reset (POR) circuit On-...