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CP82C89 Dataheets PDF



Part Number CP82C89
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description CMOS Bus Arbiter
Datasheet CP82C89 DatasheetCP82C89 Datasheet (PDF)

82C89 March 1997 CMOS Bus Arbiter Description The Intersil 82C89 Bus Arbiter is manufactured using a selfaligned silicon gate CMOS process (Scaled SAJI IV). This circuit, along with the 82C88 bus controller, provides full bus arbitration and control for multi-processor systems. The 82C89 is typically used in medium to large 80C86 or 80C88 systems where access to the bus by several processors must be coordinated. The 82C89 also provides high output current and capacitive drive to eliminate the n.

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82C89 March 1997 CMOS Bus Arbiter Description The Intersil 82C89 Bus Arbiter is manufactured using a selfaligned silicon gate CMOS process (Scaled SAJI IV). This circuit, along with the 82C88 bus controller, provides full bus arbitration and control for multi-processor systems. The 82C89 is typically used in medium to large 80C86 or 80C88 systems where access to the bus by several processors must be coordinated. The 82C89 also provides high output current and capacitive drive to eliminate the need for additional bus buffering. Static CMOS circuit design insures low operating power. The advanced Intersil SAJI CMOS process results in performance equal to or greater than existing equivalent products at a significant power savings. Features • Pin Compatible with Bipolar 8289 • Performance Compatible with: - 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz) • Provides Multi-Master System Bus Control and Arbitration • Provides Simple Interface with 82C88/8288 Bus Controller • Synchronizes 80C86/8086, 80C88/8088 Processors with Multi-Master Bus • Bipolar Drive Capability • Four Operating Modes for Flexible System Configuration • Low Power Operation - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA (Max) - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . .1mA/MHz (Max) • Operating Temperature Ranges - C82C89 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC - I82C89 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC - M82C89 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Ordering Information PART NUMBER CP82C89 IP82C89 CS82C89 IS82C89 CD82C89 ID82C89 MD82C89/B 5962-8552801RA MR82C89/B 5962-85528012A SMD# 20 Pad CLCC SMD# -55oC to +125oC 20 Ld CERDIP 20 Ld PLCC PACKAGE 20 Ld PDIP TEMPERATURE RANGE 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC -55oC to +125oC PKG. NO. E20.3 E20.3 N20.35 N20.35 F20.3 F20.3 F20.3 F20.3 J20.A J20.A Pinouts 82C89 (CERDIP) TOP VIEW S2 IOB SYSB/RESB RESB BCLK INIT BREQ BPRO BPRN 1 2 3 4 5 6 7 8 9 20 VCC 19 S1 18 S0 17 CLK 16 LOCK INIT 15 CRQLCK BREQ 14 ANYRQST 13 AEN 12 CBRQ 11 BUSY BPRO 6 7 8 9 BPRN 10 GND 11 BUSY 12 CBRQ 13 AEN RESB BCLK 4 5 18 S0 17 CLK 16 LOCK 15 CRQLCK 14 ANYRQST 82C89 (PLCC, CLCC) TOP VIEW SYSB/ RESB VCC 20 IOB S2 3 2 1 19 GND 10 S1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 2980.1 4-343 82C89 Functional Diagram ARBITRATION MULTIBUS INTERFACE STATUS DECODER 80C86/ 80C88 STATUS S2 S1 S0 INIT BCLK BREQ BPRN BPRO BUSY CBRQ MULTIBUSTM COMMAND SIGNALS CONTROL/ STRAPPING OPTIONS LOCK CLK CRQLCK RESB ANYRQST IOB CONTROL LOCAL BUS INTERFACE AEN SYSB/ RESB SYSTEM SIGNALS +5V GND MULTIBUSTM IS AN INTEL CORP. TRADEMARK Pin Description PIN SYMBOL VCC NUMBER 20 TYPE DESCRIPTION VCC: The +5V Power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for decoupling. GROUND. I STATUS INPUT PINS: The status input pins from an 80C86, 80C88 or 8089 processor. The 82C89 decodes these pins to initiate bus request and surrender actions. (See Table 1). CLOCK: From the 82C84A or 82C85 clock chip and serves to establish when bus arbiter actions are initiated. LOCK: A processor generated signal which when activated (low) prevents the arbiter from surrendering the multi-master system bus to any other bus arbiter, regardless of its priority. COMMON REQUEST LOCK: An active low signal which prevents the arbiter from surrendering the multi-master system bus to any other bus arbiter requesting the bus through the CBRQ input pin. RESIDENT BUS: A strapping option to configure the arbiter to operate in systems having both a multi-master system bus and a Resident Bus. Strapped high, the multi-master system bus is requested or surrendered as a function of the SYSB/RESB input pin. Strapped low, the SYSB/RESB input is ignored. ANY REQUEST: A strapping option which permits the multi-master system bus to be surrendered to a lower priority arbiter as if it were an arbiter of higher priority (i.e., when a lower priority arbiter requests the use of the multi-master system bus, the bus is surrendered as soon as it is possible). When ANYRQST is strapped low, the bus is surrendered according to Table A in Design Information. If ANYRQST is strapped high and CBRQ is activated, the bus is surrendered at the end of the present bus cycle. Strapping CBRQ low and ANYRQST high forces the 82C89 arbiter to surrender the multi-master system bus after each transfer cycle. Note that when surrender occurs BREQ is driven false (high). GND S0, S1, S2 10 1, 18-19 CLK 17 I LOCK 16 I CRQLCK 15 I RESB 4 I ANYRQST 14 I 4-344 82C89 Pin Description PIN SYMBOL IOB (Continued) NUMBER 2 TYPE I DESCRIPTION IO BUS: A strapping option which configures the 82C89 Arbiter to operate in systems having both .


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