IS45S32400E

IS42S32400E IS45S32400E 4M x 32 128Mb SYNCHRONOUS DRAM NOVEMBER 2010 FEATURES Clock frequency: 166, 143, 133 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge Single Power supply: 3.3V + 0.3V LVTTL interface Programmable burst length – (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Auto Refresh (CBR) Self Refresh 4096 refresh cycles every 16ms (A2 grade) or 64 ms (Commercial, Industrial, A1 grade) Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command OPTIONS Package: 86-pin TSOP-II 90-ball TF-BGA Operating Temperature Range: Commercial (0oC to +70oC) Industrial (-40oC to +85oC) Automotive Grade, A1 (-40oC to +85oC) Automotive Grade, A2 (-40oC to +105oC) OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 -7 6 7 10 10 166 143 100 100 5.4 5.4 6.5 6.5 -75E Unit –...