IS45S32160B

IS42S32160B IS45S32160B 16M x 32 512Mb SYNCHRONOUS DRAM PRELIMINARY INFORMATION JULY 2009 FEATURES Clock frequency: 166, 143 MHz Fully synchronous; all signals referenced to a positive clock edge Internal bank for hiding row access/precharge Single Power supply: 3.3V + 0.3V LVTTL interface Programmable burst length – (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Auto Refresh (CBR) Self Refresh 8192 refresh cycles every 16ms (A2 grade) or 64 ms (Commercial, Industrial, A1 grade) Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command OPTIONS Package: 86-pin TSOP-II 90-ball W-BGA Operating Temperature Range: Commercial (0oC to +70oC) Industrial (-40oC to +85oC) Automotive Grade, A1 (-40oC to +85oC) Automotive Grade, A2 (-40oC to +105oC) Die Revision: B OVERVIEW ISSI's 512Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 512Mb SDRAM is organized in 4Meg x 32 bit x 4 Banks. KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 -7 -75E Unit 6 7 — ns 10 10 7.5 ns 166 ...