Family of 16-bit CAN-enabled CompactRISC Microcontrollers
CR16HCS5/CR16HCS9/CR16MAR5/CR16MAS5 CR16MAS9/CR16MBR5/CR16MCS5/CR16MCS9 Family of 16-bit CAN-enabled CompactRISC Microco...
Description
CR16HCS5/CR16HCS9/CR16MAR5/CR16MAS5 CR16MAS9/CR16MBR5/CR16MCS5/CR16MCS9 Family of 16-bit CAN-enabled CompactRISC Microcontrollers
January 2002
CR16HCS5/CR16HCS9/CR16MAR5/CR16MAS5 CR16MAS9/CR16MBR5/CR16MCS5/CR16MCS9 Family of 16-bit CAN-enabled CompactRISC Microcontrollers
1.0 General Description
plex Instruction Set Computer (CISC): compact code, onchip memory and I/O, and reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 25 million instructions per second (MIPS) at a clock rate of 24 MHz. The device contains a FullCAN class, CAN serial interface for low/high speed applications with 15 orthogonal message buffers, each supporting standard as well as extended message identifiers. The family of 16-bit CompactRISCâ„¢ microcontroller is based on a Reduced Instruction Set Computer (RISC) architecture. The device operates as a complete microcomputer with all system timing, interrupt logic, flash program memory or ROM memory, RAM, EEPROM data memory, and I/O ports included on-chip. It is ideally suited to a wide range of embedded controller applications because of its high performance, on-chip integrated features and low power consumption resulting in decreased system cost. The device offers the high performance of a RISC architecture while retaining the advantages of a traditional Com-
Block Diagram
Fast Clk Slow Clk* CR16CAN FullCAN 2.0B Clock Generator Power-on-Reset
CR16B RISC Core
Processing ...
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