Document
CR16HCS5/CR16HCS9/CR16MAR5/CR16MAS5 CR16MAS9/CR16MBR5/CR16MCS5/CR16MCS9 Family of 16-bit CAN-enabled CompactRISC Microcontrollers
January 2002
CR16HCS5/CR16HCS9/CR16MAR5/CR16MAS5 CR16MAS9/CR16MBR5/CR16MCS5/CR16MCS9 Family of 16-bit CAN-enabled CompactRISC Microcontrollers
1.0 General Description
plex Instruction Set Computer (CISC): compact code, onchip memory and I/O, and reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 25 million instructions per second (MIPS) at a clock rate of 24 MHz. The device contains a FullCAN class, CAN serial interface for low/high speed applications with 15 orthogonal message buffers, each supporting standard as well as extended message identifiers. The family of 16-bit CompactRISC™ microcontroller is based on a Reduced Instruction Set Computer (RISC) architecture. The device operates as a complete microcomputer with all system timing, interrupt logic, flash program memory or ROM memory, RAM, EEPROM data memory, and I/O ports included on-chip. It is ideally suited to a wide range of embedded controller applications because of its high performance, on-chip integrated features and low power consumption resulting in decreased system cost. The device offers the high performance of a RISC architecture while retaining the advantages of a traditional Com-
Block Diagram
Fast Clk Slow Clk* CR16CAN FullCAN 2.0B Clock Generator Power-on-Reset
CR16B RISC Core
Processing Unit
Core Bus
Peripheral Bus Controller
64k-Byte Flash Program Memory
3k-Byte RAM
2176-Byte 1.5k-Byte ISP EEPROM Memory Data Memory
Interrupt
Control
Power Management
Timing and Watchdog
Peripheral Bus
I/O
µWire/SPI
2x USART
ACCESS bus
4x VTU
2x MFT
12-ch 8-bit A/D
MIWU
2 Analog Comparators
Please note that not all family members contain same peripheral modules and features.
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Table of Contents
1.0 2.0 3.0 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 CR16B CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.4 Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.6 Multi-Input Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.7 Dual Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . 6 3.8 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.9 Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . 6 3.10 Versatile timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.11 Real-Time TIMER and Watchdog . . . . . . . . . . . . . . 6 3.12 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.13 MICROWIRE/SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.14 CR16CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.15 ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . 7 3.16 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.17 Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . 7 3.18 Development Support . . . . . . . . . . . . . . . . . . . . . . . 7 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 ENV0 and ENV1 Pins . . . . . . . . . . . . . . . . . . . . . . 12 5.2 Module Configuration (MCFG) Register . . . . . . . . 12 5.3 Module Status (MSTAT) Register . . . . . . . . . . . . . 12 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 Open-Drain Operation . . . . . . . . . . . . . . . . . . . . . . 14 CPU and Core Registers . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 General-Purpose Registers . . . . . . . . . . . . . . . . . . 15 7.2 Dedicated Address Registers . . . . . . . . . . . . . . . . 15 7.3 Processor Status Register . . . . . . . . . . . . . . . . . . . 15 7.4 Configuration Register . . . . . . . . . . . . . . . . . . . . . . 16 7.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.6 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.7 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bus Interface Unit . . . . . . . . . . . . . . . . . . ..