ARM DataSheet

STMicroelectronics

STM32F103C8T6 - ARM-based 32-bit MCU

36 Hits • ARM® 32-bit Cortex®-M3 CPU Core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle

STMicroelectronics

STM32F407 - Arm 32-bit Cortex-M4 CPU

36 Hits • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequ

STMicroelectronics

STM32F429 - ARM Cortex-M4 32-bit MCU+FPU

29 Hits • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, fre

STMicroelectronics

STM32F405RG - Arm 32-bit Cortex-M4 CPU

24 Hits • Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequ

STMicroelectronics

STM32L432KC - Ultra-low-power Arm Cortex-M4 32-bit MCU+FPU

23 Hits • Ultra-low-power with FlexPowerControl – 1.71 V to 3.6 V power supply – -40 °C to 85/105/125 °C temperature range – 8 nA Shutdown mode (2 wakeup pins

STMicroelectronics

STM32F105VC - ARM-based 32-bit MCU

23 Hits FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-

STMicroelectronics

STM32F105VB - ARM-based 32-bit MCU

23 Hits FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-

NXP Semiconductors

LPC1769 - 32-bit ARM Cortex-M3 microcontroller

23 Hits

STMicroelectronics

STM32F105RC - ARM-based 32-bit MCU

20 Hits FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-

NXP

LPC11U23 - 32-bit ARM Cortex-M0 microcontroller

16 Hits and benefits  System:  ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.  ARM Cortex-M0 built-in Nested Vectored Interrupt Controlle

Knowles Electronics

TWFK-30017-000 - Balanced Armature Driver

15 Hits • Best-in-class treble • HD Audio to 40kHz • Also midrange-tweeter in hybrids • Small size • RoHS compliant Outline Drawing mm (inches) Demons

Unisonic Technologies

LM8560 - DIGITAL ALARM CLOCK

14 Hits *Single chip P-channel ED MOS LSI *LED direct drive using time division (duplex configuration) *Wide operating power supply voltage range *Built-in al

NXP

LPC1788 - (LPC177x / LPC178x) 32-bit ARM Cortex-M3 microcontroller

14 Hits and a higher level of support block integration. The Cortex-M3 CPU incorporates a 3-stage pipeline and has a Harvard architecture with separate local

GigaDevice

GD32F103 - ARM Cortex-M3 32-bit MCU

14 Hits . 9 2.3. Pinouts and pin assignment ........ 11 2.

STMicroelectronics

STM32F105V8 - ARM-based 32-bit MCU

13 Hits FBGA • Core: ARM 32-bit Cortex -M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-

ATMEL

SAM9G45 - AT91SAM ARM-based Embedded MPU

13 Hits the frequently demanded combination of user interface functionality and high data rate connectivity, including LCD controller, resistive touchscreen,

ETC

ARM7TDMI - general purpose 32-bit microprocessors

12 Hits his datasheet, or any error or omission in such information, or any incorrect use of the product. Change Log Issue A (Draft 0.1) (Draft 0.2) B C D dr

STMicroelectronics

STM32F103C8 - ARM-based 32-bit MCU

12 Hits Includes ST state-of-the-art patented technology • Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performa

STMicroelectronics

STM32H743AI - 32-bit Arm Cortex-M7 480MHz MCUs

12 Hits Includes ST state-of-the-art patented technology Core • 32-bit Arm® Cortex®-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data and 16 Kb

Hynix Semiconductor

HMS30C7202 - 32-bit ARM7TDMI RISC static CMOS CPU core

11 Hits 32-bit ARM7TDMI RISC static CMOS CPU core : Running up to 70 MHz 8Kbytes combined instruction/data cache Memory management unit Supports L

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