| No. | Part # | Manufacturer | Description | Datasheet |
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Cypress Semiconductor |
(GVT7xxxx) 256K x 36 / 512K x 18 Sunchronous Burse Flowthrough SRAM • • • • • • • • • • • Fast access times: 6.0, 6.5, 7.0, and 8.0 ns Fast clock speed: 150, 133, 117, and 100 MHz 1 ns set-up time and hold time Fast OE access times: 3.5 ns and 4.0 ns 3.3V –5% and +10% power supply 3.3V or 2.5V I/O supply 5V tolerant |
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Cypress Semiconductor |
(GVT7xxxx) 256K X 36/512K X 18 Pipelined SRAM • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns • Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and 150 MHz • Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns • Optimal for performance (two cycle chip deselect, depth expansion without wait state) • 3. |
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Cypress Semiconductor |
(GVT7xxxx) 256K x 36 / 512K x 18 Pipelined SRAM • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns Optimal for depth expansion (one cycle chip deselect to eliminate bus cont |
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Cypress Semiconductor |
(GVT7xxxx) 256K x 36 / 512K x 18 Flow Thru SRAM • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 133, 117, and 100 MHz • Fast access time: 6.5, 7.0, 7.5, and 8.0 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% a |
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Cypress Semiconductor |
(GVT7xxxx) 256K x 36 / 512K x 18 Flow Thru SRAM • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 133, 117, and 100 MHz • Fast access time: 6.5, 7.0, 7.5, and 8.0 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% a |
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Cypress Semiconductor |
(GVT7xxxx) 256K x 36 / 512K x 18 Flow Thru SRAM • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 133, 117, and 100 MHz • Fast access time: 6.5, 7.0, 7.5, and 8.0 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% a |
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Cypress Semiconductor |
(GVT7xxxx) 256K x 36 / 512K x 18 Pipelined SRAM • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns Optimal for depth expansion (one cycle chip deselect to eliminate bus cont |
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Cypress Semiconductor |
(GVT7xxxx) 256K x 36 / 512K x 18 Sunchronous Burse Flowthrough SRAM • • • • • • • • • • • Fast access times: 6.0, 6.5, 7.0, and 8.0 ns Fast clock speed: 150, 133, 117, and 100 MHz 1 ns set-up time and hold time Fast OE access times: 3.5 ns and 4.0 ns 3.3V –5% and +10% power supply 3.3V or 2.5V I/O supply 5V tolerant |
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Cypress Semiconductor |
(GVT7xxxx) 256K x 36 / 512K x 18 Sunchronous Burse Flowthrough SRAM • • • • • • • • • • • Fast access times: 6.0, 6.5, 7.0, and 8.0 ns Fast clock speed: 150, 133, 117, and 100 MHz 1 ns set-up time and hold time Fast OE access times: 3.5 ns and 4.0 ns 3.3V –5% and +10% power supply 3.3V or 2.5V I/O supply 5V tolerant |
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Cypress Semiconductor |
(GVT7xxxx) 256K x 36 / 512K x 18 Pipelined SRAM • • • • • • • • • • • • • • • • • • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns Fast clock speed: 225, 200, 166, and 150 MHz Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns Optimal for depth expansion (one cycle chip deselect to eliminate bus cont |
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Cypress Semiconductor |
(GVT71256E18 / GVT7C1325A) 256K x 18 Synchronous Flow Through Burst SRAM • • • • • • • • • • • • • • • • Fast access times: 7.5 and 8 ns Fast clock speed: 117 and 100 MHz Provide high-performance 2-1-1-1 access rate Fast OE access times: 4.0 ns 3.3V –5% and +10% power supply 2.5V or 3.3V I/O supply 5V tolerant inputs exce |
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Cypress Semiconductor |
(GVT71256T18 / GVT7C1359A) 256K X 18 Synchronous-pipelined Cache Tag RAM • • • • • • • • • • • • • • • • • • • Fast match times: 3.5, 3.8, 4.0 and 4.5 ns Fast clock speed: 166, 150, 133, and 100 MHz Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns Pipelined data comparator Data input register load control by DEN Optimal for |
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Cypress Semiconductor |
(GVT7xxxx) 256Kx36/512Kx18 Pipelined SRAM With Nobltm Architecture • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 166, 133, 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% and |
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Cypress Semiconductor |
(GVT7xxxx) 256Kx36/512Kx18 Pipelined SRAM With Nobltm Architecture • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 166, 133, 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% and |
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Cypress Semiconductor |
(GVT7xxxx) 256Kx36/512Kx18 Pipelined SRAM With Nobltm Architecture • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 166, 133, 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% and |
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Cypress Semiconductor |
(GVT7xxxx) 256K X 36/512K X 18 Pipelined SRAM • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns • Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and 150 MHz • Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns • Optimal for performance (two cycle chip deselect, depth expansion without wait state) • 3. |
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Cypress Semiconductor |
(GVT7xxxx) 256K X 36/512K X 18 Pipelined SRAM • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns • Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and 150 MHz • Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns • Optimal for performance (two cycle chip deselect, depth expansion without wait state) • 3. |
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Cypress Semiconductor |
(GVT7xxxx) 256K X 36/512K X 18 Pipelined SRAM • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns • Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and 150 MHz • Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns • Optimal for performance (two cycle chip deselect, depth expansion without wait state) • 3. |
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Cypress Semiconductor |
(GVT71256T18 / GVT7C1359A) 256K X 18 Synchronous-pipelined Cache Tag RAM • • • • • • • • • • • • • • • • • • • Fast match times: 3.5, 3.8, 4.0 and 4.5 ns Fast clock speed: 166, 150, 133, and 100 MHz Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns Pipelined data comparator Data input register load control by DEN Optimal for |
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Cypress Semiconductor |
(GVT7xxxx) 256Kx36/512Kx18 Pipelined SRAM With Nobltm Architecture • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 166, 133, 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns • Internally synchronized registered outputs eliminate the need to control OE • Single 3.3V –5% and |
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