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nexperia |
Octal D-type transparent latch latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches |
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nexperia |
Quad 2-input AND gate and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Input levels: • For 74HC08: CMOS level • For 74HCT08: TTL level • Com |
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nexperia |
shift register two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH |
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nexperia |
serial or parallel-out shift register a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is trans |
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nexperia |
Dual buffer/line driver and benefits • Wide supply voltage range from 2.0 V to 6.0 V • Input levels: • For 74HC2G125: CMOS level • For 74HCT2G125: TTL level • Symmetrical output impedance • High noise immunity • Low power dissipation • Balanced propagation delays • ESD prot |
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nexperia |
3-to-8 line decoder/demultiplexer three enable inputs (E1 and E2 and E3). Every output will be LOW unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '238 ICs and one inverter. The |
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nexperia |
14-stage binary ripple counter and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2. |
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nexperia |
Dual retriggerable monostable multivibrator and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2. |
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nexperia |
Dual 4-channel analog multiplexer/demultiplexer four independent inputs/outputs (nY0, nY1, nY2 and nY3) and a common input/output (nZ). A digital enable input (E) and two digital select inputs (S0 and S1) are common to both switches. When E is HIGH, the switches are turned off. Inputs include clam |
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nexperia |
Dual D-type flip-flop and benefits • Wide supply voltage range from 2.0 to 6.0 V • CMOS low power dissipation • High noise immunity • Input levels: • For 74HC74: CMOS level • For 74HCT74: TTL level • Symmetrical output impedance • High noise immunity • Balanced propagatio |
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nexperia |
Hex inverting Schmitt trigger reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly ch |
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nexperia |
Octal bus transceiver an output enable (OE) and send/receive (DIR) for direction control. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages |
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nexperia |
Quad D-type flip-flop clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on |
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nexperia |
Dual 4-input multiplexer independent enable inputs (nE) and common data select inputs (S0 and S1). For each multiplexer, the select inputs select one of the four binary inputs and routes it to the multiplexer output (nY). A HIGH on E forces the corresponding multiplexer outp |
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nexperia |
Octal bus transceiver an output enable (OE) and send/receive (DIR) for direction control. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages |
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nexperia |
Triple 3-input OR gate and benefits • Complies with JEDEC standard no. 7A • Input levels: • For 74HC4075: CMOS level • For 74HCT4075: TTL level • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • Specified from -40 °C to +85 °C and from - |
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nexperia |
Quad 2-input NOR gate and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Input levels: • For 74HC02: CMOS level • For 74HCT02: TTL level • Com |
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nexperia |
Quad 2-input EXCLUSIVE-OR gate and benefits • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2. |
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nexperia |
Dual retriggerable monostable multivibrator and benefits • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C • Wide supply voltage range from 2.0 V to 6.0 V • CMOS low power dissipation • High noise immunity • La |
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nexperia |
Quad D-type flip-flop clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on |
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