TPS3837J25

TPS3837J25-EP : The TPS3836, TPS3837, TPS3838 families of supervisory circuits provide circuit initialization and timing supervision, primarily for digital signal processing (DSP) and processor-based systems. During power on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supervisory circuit monitors VDD and keeps RESET output active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time starts after VDD has risen above VIT. When CT is connected to GND, a fixed delay time of typical 10 ms is asserted. When connected to VDD, the delay time i.

TPS3837J25-Q1 : The TPS3836, TPS3837, TPS3838 families of supervisory circuits provide circuit initialization and timing supervision, primarily for DSP and processor-based systems. D Applications Include − Applications Using Automotive Low-Power DSPs, Microcontrollers, or Microprocessors − Battery-Powered Equipment − Intelligent Instruments − Wireless Communication Systems − Automotive Systems TPS3836, TPS3838 DBV PACKAGE (TOP VIEW) CT 1 5 VDD GND 2 MR 3 4 RESET TPS3837 DBV PACKAGE (TOP VIEW) CT 1 5 VDD GND 2 MR 3 4 RESET During power on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supervisory circuit monitors VDD and keeps RESET output active as long as.