SN74AHC244

SN74AHC240 : These octal buffers/drivers are designed specifically to improve the performance and density of 3-state memory-address drivers, clock drivers, and busoriented receivers and transmitters. Package Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) J (CDIP, 20) 24.2 mm × 6.92 mm SN54AHC240 W (CFP, 20) 13.09 mm × 6.92 mm FK (LCCC, 20) 8.89 mm × 8.89 mm N (PDIP, 20) 24.33 mm × 6.35 mm SN74AHC240 DW (SOIC, 20) NS (SOP, 20) 12.8 mm × 7.5 mm 12.6 mm × 5.30 mm PW (TSSOP, 20) 6.5 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safe.

SN74AHC244-EP : ordering information This octal buffer/driver is designed specifically to improve the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74AHC244 is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PACKAGE‡ ORD.

SN74AHC244-Q1 : ordering information This octal buffer/driver is designed specifically to improve the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. DW OR PW PACKAGE (TOP VIEW) 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 2OE 18 1Y1 17 2A4 16 1Y2 15 2A3 14 1Y3 13 2A2 12 1Y4 11 2A1 The SN74AHC244 is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC.

SN74AHC244Q : SN74AHC244Q OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SGDS017 – FEBRUARY 2002 DW OR PW PACKAGE (TOP VIEW) 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 2OE 18 1Y1 17 2A4 16 1Y2 15 2A3 14 1Y3 13 2A2 12 1Y4 11 2A1 This octal buffer/driver is designed specifically to improve the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74AHC244Q is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance sta.

SN74AHC245 : The SNx4AHC245 octal bus transceivers are designed for asynchronous two-way communication between data buses. This part operates from 4.5 V to 5.5 V. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) PDIP (20) 25.40 mm x 6.35 mm SSOP (20) 7.50 mm x 5.30 mm SNx4AHC245 TSSOP (20) 6.50 mm x 4.40 mm TVSOP (20) 5.00 mm x 4.40 mm SOIC (20) 12.80 mm x 7.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic 1 DIR 19 OE 2 A1 18 B1 To Seven Other Channels 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property m.

SN74AHC245-EP : ordering information The SN74AHC245 octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. This device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses effectively are isolated. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERIN.

SN74AHC245-Q1 : ordering information The SN74AHC245 octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. This device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses effectively are isolated. DW OR PW PACKAGE (TOP VIEW) DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 OE 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 B8 To ensure the high-impedance state during power up or power down, OE should b.

SN74AHC245Q : The SN74AHC245Q octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. DW OR PW PACKAGE (TOP VIEW) DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 OE 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 B8 This device allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE should be tied to VCC throu.