– 1-200 MHz Low-Power (LP) HCSL DIF pairs ▪ 9DBL0843 default Zout = 100Ω ▪ 9DBL0853 default Zout = 85Ω ▪ Easy AC-coupling to other logic families, see IDT application note AN-891. Key Specifications ▪ PCIe...
9DBL0853 PDF File
| Part Number | 9DBL0853 |
| Manufacturer | Renesas (https://www.renesas.com/) |
| Title | LP-HCSL Zero-Delay Buffer |
| Description | The 9DBL08x3 devices are 3.3V members of IDT's Full-Featured PCIe clock family. They support PCIe Gen1-4 Common Clock (CC) architectures and also ... |
| Features |
▪ Loss Of Signal (LOS) open drain output ▪ 8 – 1-200 MHz Low-Power (LP) HCSL DIF pairs ▪ 9DBL0843 default Zout = 100Ω ▪ 9DBL0853 default Zout = 85Ω ▪ Easy AC-coupling to other logic families, see IDT application note AN-891. Key Specifications ▪ PCIe... |
| Published | Jun 4, 2020 |
| Datasheet |
9DBL0853 PDF File
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