SN74AHC32

SN74AHC32-EP : ordering information The SN74AHC32 is a quadruple 2-input positive-OR gate. This device performs the Boolean function + + ) Y A • B or Y A B in positive logic. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING –55°C to 125°C SOIC – D TSSOP – PW Tape and reel Tape and reel SN74AHC32MDREP SN74AHC32MPWREP AHC32MEP AHC32EP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H X H X H H L L L Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of T.

SN74AHC32D : The ’AHC32 devices are quadruple 2-input positive-OR gates. These devices perform the Boolean function Y = A • B or Y = A + B in positive logic. FUNCTION TABLE (EACH GATE) INPUTS OUTPUT A B Y H X H X H H L L L LOGIC DIAGRAM (POSITIVE LOGIC) A Y B 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include t.

SN74AHC32N : The ’AHC32 devices are quadruple 2-input positive-OR gates. These devices perform the Boolean function Y = A • B or Y = A + B in positive logic. FUNCTION TABLE (EACH GATE) INPUTS OUTPUT A B Y H X H X H H L L L LOGIC DIAGRAM (POSITIVE LOGIC) A Y B 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include t.

SN74AHC32Q-Q1 : The SN74AHC32Q is a quadruple 2-input positive-OR gate. This device performs the Boolean function Y + A • B or Y + A ) B in positive logic. ORDERING INFORMATION{ TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 125°C SOIC − D TSSOP − PW Tape and reel Tape and reel SN74AHC32QDRQ1 SN74AHC32QPWRQ1 AHC32Q HA32Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H X H X H H L L L Please be aware that an impo.

SN74AHC367 : The ’AHC367 devices are hex buffers and line drivers designed for 2-V to 5.5-V VCC operation. These devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’AHC367 devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resisto.

SN74AHC367D : The ’AHC367 devices are hex buffers and line drivers designed for 2-V to 5.5-V VCC operation. These devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’AHC367 devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resisto.

SN74AHC367N : The ’AHC367 devices are hex buffers and line drivers designed for 2-V to 5.5-V VCC operation. These devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’AHC367 devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resisto.

SN74AHC373 : ordering information The ’AHC373 devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. ORDERING INFORMATION TA PACKAGE† ORDERABLE PA.

SN74AHC373N : ordering information The ’AHC373 devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. ORDERING INFORMATION TA PACKAGE† ORDERABLE PA.

SN74AHC374 : The SNx4AHC374 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SSOP (20) 7.50 mm × 5.30 mm TVSOP (20) 5.00 mm × 4.40 mm SNx4AHC374 SOIC (20) 12.80 mm × 7.50 mm PDIP (20) 25.40 mm × 6.35 mm TSSOP (20) 6.50 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic OE CLK C1 1Q 1D 1D To Seven Other.

SN74AHC374N : The SNx4AHC374 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SSOP (20) 7.50 mm × 5.30 mm TVSOP (20) 5.00 mm × 4.40 mm SNx4AHC374 SOIC (20) 12.80 mm × 7.50 mm PDIP (20) 25.40 mm × 6.35 mm TSSOP (20) 6.50 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic OE CLK C1 1Q 1D 1D To Seven Other.