SN54LS377

SN54LS37 : SN54/74LS37 QUAD 2-INPUT NAND BUFFER QUAD 2-INPUT NAND BUFFER VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 1.2 12 24 Unit V °C mA mA FAST AND LS TTL DATA 5-91 SN54/74LS37 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limi.

SN54LS37 : PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device 5962-9754101Q2A Status Package Type Package Pins Package (1) Drawing Qty ACTIVE LCCC FK 20 1 Eco Plan (2) TBD Lead/Ball Finish (6) POST-PLATE MSL Peak Temp (3) N / A for Pkg Type Op Temp (°C) -55 to 125 5962-9754101QCA 5962-9754101QCA 5962-9754101QDA 5962-9754101QDA SN54LS37J SN54LS37J SN54S37J SN54S37J SN74LS37N SN74LS37N SN74LS37NSR SN74LS37NSR SN74S37D SN74S37D ACTIVE CDIP ACTIVE CDIP ACTIVE CFP ACTIVE CFP ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE CDIP CDIP CDIP CDIP PDIP PDIP SO SO SOIC SOIC J 14 1 TBD A42 N / A for Pkg Type -55 to 125 J 14 1 T.

SN54LS373 : OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The SN54 / 74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable.

SN54LS373 : These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is .

SN54LS374 : OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The SN54 / 74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enabl.

SN54LS374 : These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is .

SN54LS375 : SN54/74LS375 4-BIT D LATCH The SN54/ 74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input /output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follow the input. When E goes LOW, the information present at the D input prior to its setup time will be retained at the Q outputs. 4-BIT D LATCH LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) V CC 16 D 3 15 Q 3 14 Q 3 13 E 2,3 12 Q 2 11 Q 2 10 D 2 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. J SUFFIX CERAMIC CA.

SN54LS375 : PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device SN54LS375J SN74LS375D SN74LS375D SN74LS375N SN74LS375N SNJ54LS375J SNJ54LS375J Status Package Type Package Pins Package (1) Drawing Qty ACTIVE CDIP J 16 1 Eco Plan (2) TBD ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE SOIC SOIC PDIP PDIP CDIP D 16 40 Green (RoHS & no Sb/Br) D 16 40 Green (RoHS & no Sb/Br) N 16 25 Green (RoHS & no Sb/Br) N 16 25 Green (RoHS & no Sb/Br) J 16 1 TBD ACTIVE CDIP J 16 1 TBD Lead/Ball Finish (6) Call TI NIPDAU NIPDAU NIPDAU NIPDAU Call TI Call TI MSL Peak Temp (3) N / A for Pkg Type Op Temp (°C) -55 to 125 Level-1-260C-UNLIM 0 to 70 Level-1-260C-UNLIM 0 to 70 N.

SN54LS377 : SN54LS377, SN54LS378, SN54LS379, SN74LS377, SN74LS378, SN74LS379 OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE SDLS167 – OCTOBER 1976 – REVISED MARCH 1988 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. •POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright © 1988, Texas Instruments Incorporated 1 SN54LS377, SN54LS378, SN54LS379, SN74LS377, SN74LS378, SN74LS379 OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE SDLS167 – OCTOBER 1976 – REVISED MARCH 1988 •2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 SN54L.

SN54LS378 : OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 / 74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54 / 74LS378 is a 6-Bit Register with a buffered common enable. This device is similar to the SN54 / 74LS174, but with common Enable rather than common Master Reset. The SN54 / 74LS379 is a 4-Bit Register with buffered common Enable. This device is similar to the SN54 / 74LS175 but features the common Enable rather then common Master Reset. • 8-Bit High Speed Parallel Registers • Positive Edge-.

SN54LS378 : SN54LS377, SN54LS378, SN54LS379, SN74LS377, SN74LS378, SN74LS379 OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE SDLS167 – OCTOBER 1976 – REVISED MARCH 1988 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. •POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright © 1988, Texas Instruments Incorporated 1 SN54LS377, SN54LS378, SN54LS379, SN74LS377, SN74LS378, SN74LS379 OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE SDLS167 – OCTOBER 1976 – REVISED MARCH 1988 •2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 SN54L.

SN54LS379 : OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE The SN54 / 74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable. The SN54 / 74LS378 is a 6-Bit Register with a buffered common enable. This device is similar to the SN54 / 74LS174, but with common Enable rather than common Master Reset. The SN54 / 74LS379 is a 4-Bit Register with buffered common Enable. This device is similar to the SN54 / 74LS175 but features the common Enable rather then common Master Reset. • 8-Bit High Speed Parallel Registers • Positive Edge-.

SN54LS379 : SN54LS377, SN54LS378, SN54LS379, SN74LS377, SN74LS378, SN74LS379 OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE SDLS167 – OCTOBER 1976 – REVISED MARCH 1988 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. •POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright © 1988, Texas Instruments Incorporated 1 SN54LS377, SN54LS378, SN54LS379, SN74LS377, SN74LS378, SN74LS379 OCTAL, HEX, AND QUAD D-TYPE FLIP-FLOPS WITH ENABLE SDLS167 – OCTOBER 1976 – REVISED MARCH 1988 •2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 SN54L.