| Part Number | MC92052 |
| Manufacturer | Motorola |
| Title | FTTC User Framer |
| Description | The MC92052 implements the TC sublayer of the DAVIC asymmetrical FTTC PHY specification for user devices. The MC92052 key functional blocks are de... |
| Features |
• • • • • • • • • • • • • • • • • Implements the DAVIC short-range baseband asymmetrical physical layer standard Supports a bit rate of up to 51.84 Mbit/sec downstream Provides TDMA at a bit rate of up to 6.48 Mbit/s upstream, including DAVIC Bit Rates B, C, and D Interfaces to an ATM-layer device u... |
| File Size | 40.47KB |
| Datasheet |
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MC92053 : The MC92053 implements four copies of the TC sublayer of the DAVIC asymmetrical FTTC PHY specification for network devices. The MC92053 key functional blocks are described in the paragraphs which follow. Tx UTOPIA Interface The Transmit UTOPIA interface accepts ATM cells from the ATM layer according to the UTOPIA Level 2 specification. Each cell is stored in one of the four transmit cell FIFO’s. This block uses TXCLK provided by the ATM layer. The FIFO’s are used for rate adaptation between TXCLK (the UTOPIA interface clock) and the device clock. Rx UTOPIA Interface The receive UTOPIA interface reads ATM cells from the four receive cell FIFO’s and transfers them to the ATM layer according to.