| Part Number | MCM64PC32 |
| Manufacturer | Motorola |
| Title | 256K/512K Pipelined BurstRAM Secondary Cache Module for Pentium |
| Description | 160–Lead Card Edge Pin Locations 20, 21, 22, 23, 24, 26, 28, 29, 101, 102, 103, 104, 106, 108, 109, 110 36, 116 11, 12, 13, 14, 92, 93, 94, 96 8 ... |
| Features |
Triton II chip set for auto –configuration of the cache control. • • • • • • • • • • • • • • • • Pentium –Style Burst Counter on Chip Pipelined Data Out 160 Pin Card Edge Module Address Pipeline Supported by ADSP Disabled with Ex All Cache Data and Tag I/Os are TTL Compatible Three State Outputs Byte ... |
| File Size | 180.65KB |
| Datasheet |
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MCM64PC32T : 160–Lead Card Edge Pin Locations 20, 21, 22, 23, 24, 26, 28, 29, 101, 102, 103, 104, 106, 108, 109, 110 30 Symbol A3 – A18 ADSP Type Input Input Description Address Inputs: These inputs are registered into data RAMs and must meet setup and hold times. The tag RAM addresses are not registered. Address Status Processor: Initiates READ, WRITE, or chip deselect cycle (Exception–chip deselect does not occur when ADSP is asserted and CCS is high. Burst Order Select: NC for interleaved burst counter. Tie to ground for linear burst counter. Byte Write Enable: To be used in future modules. Cache Address Status: Initiates READ, WRITE, or chip deselect cycle. Cache Burst Advance: Increments address co.