| Part Number | M312L5720BG0-CB3 |
| Manufacturer | Samsung |
| Title | DDR SDRAM Registered Module |
| Description | Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS17 CK0,CK0 ~ CK2, CK2 CKE0, CKE1(for double banks) CS0, CS1(for double banks) RAS CAS WE CB0 ~ CB... |
| Features |
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • P... |
| Published | May 2, 2005 |
| Datasheet |
 M312L5720BG0-CB3 PDF File
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