| Part Number | PM7388 |
| Manufacturer | PMC-Sierra |
| Title | Frame Engine and Datalink Manager |
| Description | Preliminary PM7388 FREEDM 336A1024 Frame Engine and Datalink Manager FEATURES • Single-chip multi-channel packet processor supporting line rate ... |
| Features |
• Single-chip multi-channel packet processor supporting line rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 336 T1s, 252 E1s, or 12 DS-3s. • Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative p... |
| File Size | 58.48KB |
| Datasheet |
|
PM7380 : .....9 PIN DIAGRAM ....12 PIN DESCRIPTION ..13 FUNCTIONAL DESCRIPTION ...38 9.1 9.2 9.3 HIGH SPEED MULTI-VENDOR INTEGRATION PROTOCOL (H-MVIP) ..38 HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL...38 RECEIVE CHANNEL ASSIGNER 39 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.
PM7381 : .....7 PIN DIAGRAM .... 11 PIN DESCRIPTION ..12 FUNCTIONAL DESCRIPTION....43 8.1 8.2 8.3 HIGH SPEED MULTI-VENDOR INTEGRATION PROTOCOL (H-MVIP) ..43 HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL...43 RECEIVE CHANNEL ASSIGNER 44 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 .
PM7382 : .....7 PIN DIAGRAM ....10 PIN DESCRIPTION .. 11 FUNCTIONAL DESCRIPTION ...36 8.1 8.2 8.3 HIGH SPEED MULTI-VENDOR INTEGRATION PROTOCOL (H-MVIP) ..36 HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL...36 RECEIVE CHANNEL ASSIGNER 37 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 .
PM7383 : .....7 PIN DIAGRAM .... 11 PIN DESCRIPTION ..12 FUNCTIONAL DESCRIPTION....44 8.1 8.2 8.3 HIGH SPEED MULTI-VENDOR INTEGRATION PROTOCOL (H-MVIP) ..44 HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL...44 RECEIVE CHANNEL ASSIGNER 45 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 .
PM7384 : .....7 PIN DIAGRAM 9 PIN DESCRIPTION ..10 FUNCTIONAL DESCRIPTION ...33 9.1 9.2 9.3 9.4 SCALEABLE BANDWIDTH INTERCONNECT (SBI) INTERFACE .....33 HIGH-LEVEL DATA LINK CONTROL (HDLC) PROTOCOL...34 SBI EXTRACTER AND PISO.35 RECEIVE CHAN.
PM7385 : changed. (See PREP #4938.) Change bars have been kept to show both Issue 4 and Issue 5 changes. Issue 6 August 2001 Patent information included. Change bars apply to previous issue. Issue 5 October 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE i PM7385 FREEDM-84A672 DATA SHEET PMC-1990114 ISSUE 6 84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE CONTENTS 1 2 3 4 5 6 7 8 FEATURES.....1 APPLICATIONS ....3 REFERENCES ....
PM7389 : Preliminary PM7389 FREEDM 84A1024 Frame Engine and Datalink Manager FEATURES • Single-chip multi-channel packet processor supporting a maximum aggregate bandwidth of 156 Mbit/s for line rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 84 T1s, 63 E1s, or 3 DS-3s. • Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative protocols supported via HDLC termination and full packet store of the data within the HDLC structure. • Support for 3 egress fragmentation sizes (128, 256, and 512 bytes) configurable on a per multilink bundle. Optionally full packet transfers are supported on a per bundle bas.