MC74F32

MC74F352 : The F352 is a dual 4-input multiplexer. It selects two bits of data from up to four sources under the control of the common Select inputs (S0, S1).The two 4-input multiplexer circuits have individual active-LOW Enables(Ea, Eb) which can be used to strobe the outputs independently. When the Enables (Ea, Eb) are HIGH, the corresponding outputs (Za, Zb) are forced HIGH. The logic equations for the outputs are shown below: The F352 can be used to move data from a group of registers to a common output bus. The particular register from which the data came would be determined by the state of the Select inputs. A less obvious application is as a function generator. The F352 can generate two function.

MC74F353 : The MC54/74F353 contains two identical 4-input multiplexers with 3-state outputs. They select two bits from four sources selected by common Select inputs (S0, S1).The 4-input multiplexers have individual Output enable (OEa, OEb) inputs which, when HIGH, force the outputs to a high impedance (high Z) state. The logic equations for the outputs are shown below: Za=OEa • (I0a • S1 • S0 +I1a • S1 • S0 + I2a • S1 • S0 + I3a • S1 • S0) Zb=OEb• (I0b • S1 • S0 + I1b • S1 • S0 + I2b•S1•S0+I3b•S1•S0) If the outputs of 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output.

MC74F365 : 11 HEX BUFFER/DRIVER GATED ENABLE NONINVERTING AND INVERTING, 3-STATE CONNECTION DIAGRAM MC54/74F365 VCC OE2 16 15 I 14 O 13 I 12 O 11 I 10 O 9 MC54/74F365 MC54/74F366 F365 HEX BUFFER/DRIVER GATED ENABLE NONINVERTING, 3-STATE F366 HEX BUFFER/DRIVER GATED ENABLE INVERTING, 3-STATE FAST™ SCHOTTKY TTL 1 OE1 2 I 3 O 4 I 5 O 6 I 7 O 8 GND 16 MC54/74F366 VCC OE2 16 15 I 14 O 13 I 12 O 11 I 10 O 9 J SUFFIX CERAMIC CASE 620-09 1 16 1 N SUFFIX PLASTIC CASE 648-08 1 OE1 2 I 3 O 4 I 5 O 6 I 7 O 8 GND 16 1 FUNCTION TABLE Inputs OE1 L L X H OE2 L L H X I L H X X O L H Z Z Outputs O H L Z Z H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance D SUFFIX SOI.

MC74F366 : 11 HEX BUFFER/DRIVER GATED ENABLE NONINVERTING AND INVERTING, 3-STATE CONNECTION DIAGRAM MC54/74F365 VCC OE2 16 15 I 14 O 13 I 12 O 11 I 10 O 9 MC54/74F365 MC54/74F366 F365 HEX BUFFER/DRIVER GATED ENABLE NONINVERTING, 3-STATE F366 HEX BUFFER/DRIVER GATED ENABLE INVERTING, 3-STATE FAST™ SCHOTTKY TTL 1 OE1 2 I 3 O 4 I 5 O 6 I 7 O 8 GND 16 MC54/74F366 VCC OE2 16 15 I 14 O 13 I 12 O 11 I 10 O 9 J SUFFIX CERAMIC CASE 620-09 1 16 1 N SUFFIX PLASTIC CASE 648-08 1 OE1 2 I 3 O 4 I 5 O 6 I 7 O 8 GND 16 1 FUNCTION TABLE Inputs OE1 L L X H OE2 L L H X I L H X X O L H Z Z Outputs O H L Z Z H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance D SUFFIX SOI.

MC74F37 : QUAD 2-INPUT NAND BUFFER MC74F37 QUAD 2-INPUT NAND BUFFER VCC 14 A 13 B 12 Y 11 A 10 B 9 Y 8 FAST™ SCHOTTKY TTL J SUFFIX CERAMIC CASE 632-08 1 A 2 B 3 Y 4 A 5 B 6 Y 7 GND 14 1 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MC74FXXJ MC74FXXN MC74FXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 74 74 74 74 Min 4.5 0 Typ 5.0 25 Max 5.5 70 –15 64 Unit V °C mA mA FAST AND LS TTL DATA 4-23 MC74F37 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Parameter Input.

MC74F373 : The F373 contains eight D-type latches with 3-state output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent; i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs one setup time preceding the HIGH-to-LOW transition of LE. The 3-state buffers are controlled by the Output Enable (OE) input. When (OE) is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode, but this does not interfere with entering new data into the latches. LOGIC DIAGRAM D0 D GO LE D1 D GO D2 .

MC74F374 : The F374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-state true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. LOGIC DIAGRAM D0 CP CP D Q Q D1 D2 D3 D4 D5 D6 D7 CP D Q Q CP D Q Q CP D Q Q CP D Q Q CP D Q Q CP D Q Q .

MC74F377 : The MC74F377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Enable (E) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The E input must be stable one setup time prior to the LOWto-HIGH clock transition for predictable operation. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — HIGH Output Current — LOW Parameter 74 74 74 74 Min 4.5 0 Typ 5.0 25 Max 5.5 70 –1.0 20 Unit V.

MC74F378 : MC54/74F378 PARALLEL D REGISTER WITH ENABLE The MC54/74F378 is a 6-bit register with a buffered common enable. This device is similar to the F174 but with common Enable rather than common Master Reset. The F378 consists of six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The Clock (CP) and Enable (E) inputs are common to all flip-flops. When the E input is LOW, new data is entered into the register on the LOWto-HIGH transition of the CP input. When the E input is HIGH the register will retain the present data independent of the CP input. This circuit is designed to prevent false clocking by transitions on the E input.. PARALLEL D REGISTER WITH ENABLE FAST™ SCHOTT.

MC74F379 : MC54/74F379 QUAD PARALLEL REGISTER The MC54/74F379 is a 4-bit register with a buffered common enable. This device is similar to the F175 but features the common Enable rather than common Master Reset. The F379 consists of four edge-triggered D-type flip-flops with individual D inputs and Q and Q outputs. The Clock (CP) and Enable (E) inputs are common to all flip-flops. When E is HIGH, the register will retain the present data independent of the CP input. The Dn and E inputs can change when the clock is in either state, provided that the recommended setup and hold times are observed. This circuit is designed to prevent false clocking by transitions on the E input. QUAD PARALLEL REGISTER WIT.

MC74F3893A : www.DataSheet4U.com MC74F3893A QUAD FUTUREBUS BACKPLANE TRANSCEIVER (3 STATE + OPEN COLLECTOR) The MC74F3893A is a quad backplane transceiver and is intended to be used in very high speed bus systems. The MC74F3893A interfaces to “Backplane Transceiver Logic” (BTL). BTL features a reduced (1 V) voltage swing for lower power consumption and a series diode on the drivers to reduce capacitive loading ( 5 pF). Incident wave switching is employed, therefore BTL propagation delays are short. Although the voltage swing is much less for BTL, so is its receiver threshold region, therefore noise margins are excellent. BTL offers low power consumption, low ground bounce, reduced EMI and crosstalk, lo.

MC74F398 : QUAD 2-PORT REGISTER The MC54/74F398 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flipflops on the rising edge of the clock. • Select Inputs from Two Data Sources • Fully Positive Edge-Triggered Operation • Both True and Complement Outputs CONNECTION DIAGRAM (TOP VIEW) VCC Qd Qd I0d I1d I1c I0c Qc Qc CP 20 19 18 17 16 15 14 13 12 11 MC54/74F398 QUAD 2-PORT REGISTER FAST™ SCHOTTKY TTL 20 1 J SUFFIX CERAMIC CASE 732-03 12 S Qa 34 Qa I0a 56 78 9 10 I1a I1b I0b Qb Qb GND LOGIC DIAGRAM I0a S D Qa I1a CP Qa I0b D Qb I1b CP Qb I0c.

MC74F399 : The MC54/74F398 is a high-speed quad 2-port register. It will select four bits of data from either of two sources (Ports) under control of a common Select input (S). The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input (CP). The 4-bit DFUNCTION TABLE Inputs S I I h h I0 I h X X I1 X X I h Output Q L H L H type output register is fully edge-triggered. The Data inputs (I0x, I1x) and Select input (S) must be stable only a setup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation. H = HIGH Voltage Level L = LOW Voltage Level h = HIGH Voltage Level one setup time prior to .