| Part Number | MN101C61 |
| Manufacturer | Panasonic Semiconductor |
| Title | Timer counter 0 : 8-bit X 1 |
| Description | MN101C61D, MN101C61G Type ROM (× 8-bit) RAM (× 8-bit) Package Minimum Instruction Execution Time Standard: MN101C61D (under development) 64 K 3K T... |
| Features |
er 0 : 8-bit × 1 (square-wave/8-bit PWM output, event count, generation of remote control carrier, pulse width measurement) Clock source · · · · · · · · · · · · · · · · · · · · · 1/2, 1/4 of system clock frequency; 1/1, 1/4, 1/16, 1/32, 1/64 of OSC oscillation clock frequency; 1/1 of XI oscillation clock frequency; ext... |
| File Size | 122.43KB |
| Datasheet |
|
MN101C61D : Sheet4U.com AM1 (MN101) Series AM1 (MN101) Series The AM1 Series of 8-bit microcomputers is the realization of developments in C programming. Because of the 8-bit architecture, which allows half-byte instruction sets and offers other advantages, assembler ROM code size can be reduced. They are compact and consume little power, but feature a shortest instruction processing time of 63 ns (5 V). They can be used in a wide variety of applications where cost performance is a demand. Features q Efficiency of C-based ROM code: Assembler rate 1 or less q High-speed instruction processing: 63 ns (32 MHz) q Linear address space: 1 MB q Identical architecture for 32- and 16-bit microcomputers q Opti.
MN101C61G : Sheet4U.com AM1 (MN101) Series AM1 (MN101) Series The AM1 Series of 8-bit microcomputers is the realization of developments in C programming. Because of the 8-bit architecture, which allows half-byte instruction sets and offers other advantages, assembler ROM code size can be reduced. They are compact and consume little power, but feature a shortest instruction processing time of 63 ns (5 V). They can be used in a wide variety of applications where cost performance is a demand. Features q Efficiency of C-based ROM code: Assembler rate 1 or less q High-speed instruction processing: 63 ns (32 MHz) q Linear address space: 1 MB q Identical architecture for 32- and 16-bit microcomputers q Opti.
MN101C62 : MN101C62D , MN101C62F Type ROM (× 8-bit) RAM (× 8-bit) Package Minimum Instruction Execution Time MN101C62D [ES (Engineering Sample) available] 64 K 2K LQFP080-P-1414A *Lead-free Standard: 0.10 µs (at 4.5 V to 5.5 V, 20 MHz) 0.25 µ s (at 2.7 V to 5.5 V, 8 MHz) 1.00 µ s (at 2.0 V to 5.5 V, 2 MHz)* 125 µ s (at 2.0 V to 5.5 V, 32 kHz)* Double speed: 0.125 µs (at 4.5 V to 5.5 V, 8 MHz) 0.25 µs (at 3.0 V to 5.5 V, 4 MHz) 62.5 µ s (at 2.0 V to 5.5 V, 32 kHz)* MN101C62F (under development) 96 K 4K * The lower limit for operation guarantee for flash memory built-in type is 2.5 V. Interrupts • Watchdog • External 0 • External 1 • External 2 • External 3 • External 4 • Timer 0 • Timer 1 • Timer 2 •.
MN101C62D : Sheet4U.com AM1 (MN101) Series AM1 (MN101) Series The AM1 Series of 8-bit microcomputers is the realization of developments in C programming. Because of the 8-bit architecture, which allows half-byte instruction sets and offers other advantages, assembler ROM code size can be reduced. They are compact and consume little power, but feature a shortest instruction processing time of 63 ns (5 V). They can be used in a wide variety of applications where cost performance is a demand. Features q Efficiency of C-based ROM code: Assembler rate 1 or less q High-speed instruction processing: 63 ns (32 MHz) q Linear address space: 1 MB q Identical architecture for 32- and 16-bit microcomputers q Opti.
MN101C62F : Sheet4U.com AM1 (MN101) Series AM1 (MN101) Series The AM1 Series of 8-bit microcomputers is the realization of developments in C programming. Because of the 8-bit architecture, which allows half-byte instruction sets and offers other advantages, assembler ROM code size can be reduced. They are compact and consume little power, but feature a shortest instruction processing time of 63 ns (5 V). They can be used in a wide variety of applications where cost performance is a demand. Features q Efficiency of C-based ROM code: Assembler rate 1 or less q High-speed instruction processing: 63 ns (32 MHz) q Linear address space: 1 MB q Identical architecture for 32- and 16-bit microcomputers q Opti.
MN101C66 : Sheet4U.com AM1 (MN101) Series AM1 (MN101) Series The AM1 Series of 8-bit microcomputers is the realization of developments in C programming. Because of the 8-bit architecture, which allows half-byte instruction sets and offers other advantages, assembler ROM code size can be reduced. They are compact and consume little power, but feature a shortest instruction processing time of 63 ns (5 V). They can be used in a wide variety of applications where cost performance is a demand. Features q Efficiency of C-based ROM code: Assembler rate 1 or less q High-speed instruction processing: 63 ns (32 MHz) q Linear address space: 1 MB q Identical architecture for 32- and 16-bit microcomputers q Opti.
MN101C67 : MN101C67D, MN101C67G Type ROM (× 8-bit) RAM (× 8-bit) Package Minimum Instruction Execution Time Standard: MN101C67D (under development) 64 K 6K TQFP080-P-1212D *Lead-free MN101C67G 128 K 10 K 0.1 µ s (at 2.5 V to 3.6 V, 20 MHz)* 0.2 µ s (at 2.1 V to 3.6 V, 10 MHz)* 0.5 µ s (at 1.8 V to 3.6 V, 4 MHz)* 62.5 µ s (at 1.8 V to 3.6 V, 32 kHz)* Double speed: 0.119 µ s (at 2.5 V to 3.6 V, 8.39 MHz)* * The operation guarantee range for flash memory built-in type is 3.0 V to 3.6 V. • RESET • Watchdog • External 0 • External 1 • External 2 • External 3 • External 4 • External 5 • Timer 0 • Timer 1 • Timer 2 • Timer 3 • Timer 4 • Timer 5 • Timer 6 • Time base • Serial 0 reception • Serial 0 transmiss.
MN101C67D : Sheet4U.com AM1 (MN101) Series AM1 (MN101) Series The AM1 Series of 8-bit microcomputers is the realization of developments in C programming. Because of the 8-bit architecture, which allows half-byte instruction sets and offers other advantages, assembler ROM code size can be reduced. They are compact and consume little power, but feature a shortest instruction processing time of 63 ns (5 V). They can be used in a wide variety of applications where cost performance is a demand. Features q Efficiency of C-based ROM code: Assembler rate 1 or less q High-speed instruction processing: 63 ns (32 MHz) q Linear address space: 1 MB q Identical architecture for 32- and 16-bit microcomputers q Opti.
MN101C67G : Sheet4U.com AM1 (MN101) Series AM1 (MN101) Series The AM1 Series of 8-bit microcomputers is the realization of developments in C programming. Because of the 8-bit architecture, which allows half-byte instruction sets and offers other advantages, assembler ROM code size can be reduced. They are compact and consume little power, but feature a shortest instruction processing time of 63 ns (5 V). They can be used in a wide variety of applications where cost performance is a demand. Features q Efficiency of C-based ROM code: Assembler rate 1 or less q High-speed instruction processing: 63 ns (32 MHz) q Linear address space: 1 MB q Identical architecture for 32- and 16-bit microcomputers q Opti.