•
•
•
•
•
•
•
•
•
•
•
•
•
•
• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is...
NT5DS128M4AF PDF File
| Part Number | NT5DS128M4AF |
| Manufacturer | Nanya Techology |
| Title | (NT5DSxxMxAF) 512Mb DDR SDRAM |
| Description | The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRA... |
| Features |
CAS Latency and Frequency
CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR333 DDR266B 6K 75B 133 100 166 133
• • • • • • • • • • • • • • • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is... |
| Published | Sep 24, 2006 |
| Datasheet |
NT5DS128M4AF PDF File
|
