| Part Number | CY7C1347D |
| Manufacturer | Cypress Semiconductor |
| Title | 128K x 36 Synchronous-Pipelined Cache SRAM |
| Description | This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technol... |
| Features |
• Fast access times: 2.5 and 3.5 ns • Fast clock speed: 250, 225, 200, and 166 MHz • 1.5-ns set-up time and 0.5-ns hold time • Fast OE access times: 2.5 ns and 3.5 ns • Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) • 3.3V –5% and +10% power supply • 3.3V or 2.5V I... |
| File Size | 574.92KB |
| Datasheet |
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CY7C1347B : The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. Logic Block Diagram CLK ADV ADSC ADSP A[16:0] GW BWE BW 3 BW2 BW1 BW0 CE1 CE2 CE3 MODE (A[1;0]) 2 BURST Q0 CE COUNTER Q1 CLR Q ADDRESS CE REGISTER D 15 17 17 15 D DQ[31:24], DP[3] Q BYTEWRITE REGISTERS D DQ[23:16], DP[2] Q BYTEWRITE REGISTERS D DQ[15:8], DP[1] Q BYTEWRITE REGISTERS D DQ[7:0], DP[0] Q BYTEWRITE REGISTERS D ENABLE CE REGISTER Q 128KX36 MEMORY ARRAY 36 36 D ENABLE DELAY Q REGISTER OE ZZ SLEEP CONTROL OUTPUT REGISTERS CLK INPUT REGISTERS CLK DQ[31:0] DP[3:0] Pentium and Intel are registered trademarks of Intel Corporation..
CY7C1347F : 1] The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 2.6 ns (250-MHz device) CY7C1347F supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC®. The burst sequence is s.
CY7C1347G : 1] The CY7C1347G is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 2.6 ns (250-MHz device). CY7C1347G supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC®. The burst sequence is .