MT5C6401

MT5C6401 : The Austin Semiconductor SRAM family employs high-speed, low-power CMOS designs using a four-transistor memory cell. Austin Semiconductor SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE\) on all organizations. This enhancement can place the outputs in High-Z for additional flexibility in system design. The X1 configuration features separate data input and output. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ goes LOW. The device offers a reduced power standby mod.

MT5C6404 : The Austin Semiconductor SRAM family employs high-speed, low-power CMOS designs using a four-transistor memory cell. Austin Semiconductor SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE\) on all organizations. This enhancement can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ goes LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve low sta.

MT5C6404 : SRAM 16Kx4 SRAM FEATURES • High speed: 9, 10, 12, 15,20 and 25ns • High-performance, low-power, CMOS double-metal process • Single +5V ±10% power supply • Easy memory expansion with CE option • All inputs and outputs are TTL-compatible OPTIONS • Timing 9ns access IOns access 12ns access 15ns access 20ns access 25ns access MARKING -9 -10 -12 -15 -20 -25 • Packages Plastic DIP (300 mil) Plastic SOJ (300 mil) • 2V data retention None DJ L • Temperature Commercial (O°C to +70°C) Industrial (-40°C to +85°C) Automotive (-40°C to +125°C) Extended (-55°C to +125°C) None IT AT XT • Part Number Example: MT5C6404DJ-15 L NOTE: Not all combinations of operating temperature, speed, data retention.

MT5C6405 : The Austin Semiconductor SRAM family employs high-speed, low-power CMOS designs using a four-transistor memory cell. Austin Semiconductor SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE\) and output enable (OE\) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW. The device offers a reduced power standby mode when disabled. This allows system desi.

MT5C6405 : SRAM 16Kx4 SRAM WITH OUTPUT ENABLE FEATURES • High speed: 9, 10, 12, 15,20 and 25ns • High-performance, low-power, CMOS double-metal process • Single +5V ±10% power supply • Easy memory expansion with CE and OE options • All inputs and outputs are TTL-compatible OPTIONS • Timing 9ns access IOns access 12ns access 15ns access 20ns access 25ns access MARKING -9 -10 -12 -15 -20 -25 • Packages Plastic DIP (300 mil) Plastic SOJ (300 mil) None DJ • 2V data retention L • Temperature Commerical (O°C to +70°C) Industrial (-40°C to +85°C) Automotive (-40°C to +125°C) Extended (-55°C to +125°C) None IT AT XT • Part Number Example: MT5C6405DJ-15 L NOTE: Not all combinations of operating tempe.

MT5C6408 : No. 108 No. 204 No. 302 The MT5C6408, 8K x 8 SRAM, employs high-speed, low-power CMOS technology, eliminating the need for clocks or refreshing. These SRAM’s have equal access and cycle times. For flexibility in high-speed memory applications, Austin Semiconductor offers dual chip enables (CE1\, CE2) and output enable (OE\) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH. Reading is accomplished when WE\ and CE2 remain HIGH and CE1\ and OE\ go LOW. The device offers a reduced power standby mode when disabled. This allows sys.

MT5C6408 : The MT5C6408 is organized as a 8,192 x 8 SRAM using a four-transistor memory cell with a high-speed, low-power CMOS process..