MT5C2561

MT5C2561 : MIC::~ON 1-· r"""'I SRAM FEATURES • High speed: 10, 12, 15,20,25 and 35ns • High-performance, low-power, CMOS double-metal process • Single +5V ±10% power supply • Easy memory expansion with CE option • All inputs and outputs are TIL-compatible OPTIONS MARKING • Timing IOns access 12nsaccess 15ns access 20ns access 25ns access 35ns access -10 -12 -15 -20 -25 -35 • Packages Plastic DIP (300 mil) Plastic SOJ (300 mil) None DJ • 2V data retention • Lowpower L P • Temperature Commercial (O°C to -t;70°C) Industrial (-40°C to +85°C) Automotive (-40°C to +125°C) Extended (-55°C to +125°C) None IT AT XT • Part Number Example: MT5C2561DJ-15 P NOTE: Not all combinations of operating tempe.

MT5C2564 : The Austin Semiconductor SRAM family employs high-speed, low-power CMOS and are fabricated using doublelayer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE\) on all organizations. This enhancement can place the outputs in High-Z for additional flexibility in system design. The x4 configuration features common data input and output. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ goes LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby powe.

MT5C2564 : The MT5C2564 is organized as a 65,536 x 4 SRAM using a four-transistor memory cell with a high-speed, low-power CMOS proc.

MT5C2565 : The Austin Semiconductor SRAM family employs high-speed, low-power CMOS designs using a four-transistor memory cell. Austin Semiconductor SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE\) and output enable (OE\) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW. The device offers a reduced power standby mode when disabled. This allows system desi.

MT5C2565 : The MT5C2565 is organized as a 65,536 x 4 SRAM using a four-transistor memory cell with a high-speed, low-power.

MT5C2568 : 32K x 8 SRAM SRAM MEMORY ARRAY AVAILABLE AS MILITARY SPECIFICATIONS •SMD 5962-88662 •SMD 5962-88552 •MIL-STD-883 FEATURES • Access Times: 12, 15, 20, 25, 35, 45, 55, 70, & 100ns • Battery Backup: 2V data retention • Low power standby • High-performance, low-power CMOS double-metal process • Single +5V (+10%) Power Supply • Easy memory expansion with CE\ • All inputs and outputs are TTL compatible OPTIONS • Timing 12ns access 15ns access 20ns access 25ns access 35ns access 45ns access 55ns access1 70ns access1 100ns access MARKING -12 -15 -20 -25 -35 -45 -55 -70 -100 • Package(s)2 Ceramic DIP (300 mil) Ceramic DIP (600 mil) Ceramic LCC (28 leads) Ceramic LCC (32 leads) Ceramic Flat Pack Ce.

MT5C2568 : The Austin Semiconductor SRAM family employs high-speed, low power CMOS designs using a four-transistor memory cell. These SRAMs are fabricated using double-layer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, Austin Semiconductor offers chip enable (CE\) and output enable (OE\) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH and CE\ and OE\ go LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve .

MT5C2568 : The MT5C2568 is organized as a 32,768 x 8 SRAM using a four-transistor memory cell with a high-speed, low-power .

MT5C2568-883C : .

MT5C256K16B2 : ADVANCE SRAM FEATURES • High speed: 12, 15,20, 25 and 35ns • Multiple center power and ground pins for improved noise immunity • Single +5V ±10% power supply • Easy memory expansion with chip enable (CE) and output enable (OE) options • All inputs and outputs are TTL-compatible • Automatic CE power-down • Fast OE access time: 6, 8, 10, 12 and 15ns • High-performance, low-power, CMOS double-metal process OPTIONS MARKING • Timing 12ns access 15ns access 20ns access 25ns access 35ns access -12 -15 -20 -25 -35 • Packages Plastic SOJ (400 mil) Plastic TSOP (400 mil) DJ TG • 2V data retention • Lowpower L P • Temperature Commercial (O°C to +70°C) Industrial (-40°C to +85°C) Automotive (.

MT5C256K4A : MIC:RON 1-· ~'c,' PRELIMINARY MT5C256K4A1 REVOLUTIONARY PINOUT 256K x 4 SRAM SRAM FEATURES • High speed: 12, 15,20 and 25ns • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • Automatic CE power down • All inputs and outputs are TTL-compatible • High-performance, low-power, CMOS double-metal process • Single +5V ±10% power supply • Fast OE access times: 6, 8, 10 and 12ns OPTIONS • Timing 12ns access 15ns access 20ns access 25ns access MARKING -12 -15 -20 -25 • Packages 32-pin SOJ (400 mil) DJ • 2V data retention • Temperature Commercial (O°C to +70°C) Industrial (-40°C to +85°C) Automotive (-40°C to +125°C) Extended (-55.