| Part Number | PM73122 |
| Manufacturer | PMC-Sierra |
| Title | 32 LINK CES/DBCES AAL1 SAR PROCESSOR |
| Description | of the floating CAS nibble capability. (SHIFT_CAS). Added more functional detail. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS C... |
| Features |
... 3 APPLICATIONS ... 9 REFERENCES... 10...
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| File Size | 4.55MB |
| Datasheet |
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PM73121 : in section 7.8.12 “R_OAM_QUEUE”, on page 163. • Removed “Preliminary” from the headers. • Removed the “P” suffix from the part number in Appendix 29, “Ordering Information”, on page 205. • Changed the following timing parameters: • Interrupt Timing: PROC_INTR Tq(max) from 16.5 ns to 17 ns. • Microprocessor RAM Read Cycle: /MEM_CS Tq(max) from 17.7 ns to 18 ns. • Microprocessor RAM Read Cycle: Tqmoe(max) from 24.7 ns to 25 ns. • Microprocessor RAM Write Cycle: /PROC_ACK Tq(max) from 17.5 ns to 18 ns. • Microprocessor RAM Write Cycle: /MEM_CS Tq(max) from 17.7 ns to 18 ns. • Microprocessor Write Command Register: /PROC_ACK Tq(max) from 17.5 ns to 18 ns. • Transmit Side Interface: RL_SER Th(min.
PM73123 : PM73123 www.DataSheet4U.com AAL1gator™-8 8 Link CES/DBCES AAL1 SAR FEATURES • Supports eight structured/unstructured T1, E1 links or one unstructured DS3, E3 or STS-1/STM-0 link over an AAL1 CBR ATM network. • Compliant with ATM Forum's CES (AFVTOA-0078), and ITU-T I.363.1. • Supports up to 256 VCs. • Supports n x 64 (consecutive channels) and m x 64 (nonconsecutive channels) structured data format with channel associated signaling (CAS) support. • Internal E1/T1 clock synthesizers provided for each line which can be controlled via internal synchronous residual time stamp (SRTS) or an internal programmable weighted moving average adaptive clocking algorithm in unstructured mode. Clock synthe.
PM73124 : Preliminary PM73124 www.DataSheet4U.com AAL1gator™-4 4 Link CES/DBCES AAL1 SAR FEATURES • Supports four structured/unstructured T1 or E1 links, or one unstructured DS3, E3 or STS-1/STM-0 link over an AAL1 CBR ATM network. • Compliant with ATM Forum's CES (AFVTOA-0078), and ITU-T I.363.1. • Supports up to 128 VCs. • Supports n x 64 (consecutive channels) and m x 64 (nonconsecutive channels) structured data format with channel associated signaling (CAS) support. • Internal E1/T1 clock synthesizers provided for each line which can be controlled via internal synchronous residual time stamp (SRTS) or an internal programmable weighted moving average adaptive clocking algorithm in unstructured mo.