Part Number
|
IS61QDPB42M18A2 |
Manufacturer
|
ISSI |
Description
|
36Mb QUADP (Burst 4) SYNCHRONOUS SRAM |
Published
|
Jun 10, 2016 |
Detailed Description
|
IS61QDPB42M18A/A1/A2 IS61QDPB41M36A/A1/A2
2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
J...
|
Datasheet
|
IS61QDPB42M18A2
|
Overview
IS61QDPB42M18A/A1/A2 IS61QDPB41M36A/A1/A2
2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM
(2.
5 Cycle Read Latency)
JANUARY 2015
FEATURES
DESCRIPTION
1Mx36 and 2Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.
5 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two echo clocks (CQ and CQ#) that are del...
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