IS61QDB24M18A IS61QDB22M36A 4Mx18, 2Mx36 72Mb QUAD (Burst 2) Synchronous SRAM AUGUST 2014 FEATURES  2Mx36 and 4Mx18 configuration available.
 On-chip Delay-Locked loop (DLL) for wide data valid window.
 Separate independent read and write ports with concurrent read and write operations.
 Synchronous pipeline read with EARLY write operation.
 Double Data Rate (DDR) interface for read and write input ports.
 Fixed 2-bit burst for read and write operations.
 Clock stop support.
 Two input clocks (K and K#) for address and control registering at rising edges only.
 Two output clocks (C and C#) for data output control.
 Two echo clocks (CQ and CQ#) that are delivered simultaneously w...

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