Part Number
|
IS61QDB41M18A |
Manufacturer
|
ISSI |
Description
|
18Mb QUAD (Burst 4) SYNCHRONOUS SRAM |
Published
|
Jun 10, 2016 |
Detailed Description
|
IS61QDB41M18A IS61QDB451236A
1Mx18, 512Kx36 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM
FEATURES
DESCRIPTION
OCTOBER 2014
...
|
Datasheet
|
IS61QDB41M18A
|
Overview
IS61QDB41M18A IS61QDB451236A
1Mx18, 512Kx36 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM
FEATURES
DESCRIPTION
OCTOBER 2014
512Kx36 and 1Mx18 configuration available.
On-chip Delay-Locked loop (DLL) for wide data valid
window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and write input ports.
1.
5 cycle read latency.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control
registering at rising edges only.
Two output clocks (C and C#) for data output control.
Two echo clocks (CQ ...
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