Part Number
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ADSP-SC589 |
Manufacturer
|
Analog Devices |
Description
|
SHARC+ Dual-Core DSP |
Published
|
Jun 23, 2016 |
Detailed Description
|
SHARC+ Dual-Core DSP with Arm Cortex-A5
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
SYSTEM FEATURES
Dual...
|
Datasheet
|
ADSP-SC589
|
Overview
SHARC+ Dual-Core DSP with Arm Cortex-A5
ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587
SYSTEM FEATURES
Dual enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short-word, word, long-word addressed
Arm Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache/32 kB L1 data cache 256 kB Level 2 (L2) cache with parity
Powerful DMA system On-chip memory protection Integrated safety features
19 mm × 19 mm 349/529 BGA (0.
8 pitch), RoHS complia...
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